International Business Machines Corporation

Infineon Technologies Ag

Globalfoundries Inc.

Samsung Electronics Co., Ltd.

Infineon Technologies North America Corp.

Oh-Jung Kwon

Paul Christian Parries

Junedong Lee

Dominic Joseph Schepis

Rishikesh Krishnan

Hongwen Yan

O Sung Kwon

Geng Wang

Chengwen Pei

Michael Patrick Chudzik

Ravikumar Ramachandran

Babar Ali Khan

Deok-kee Kim

Kenneth T Settlemyer, Jr

Seong-Dong Kim

Donghun Kang

Min-Soo Kim

Yun Yu Wang

Subramanian Srikanteswara Iyer

Herbert Lei Ho

Zhengwen O Li

Conal Eugene Murray

Siddarth A Krishnan

Ravi Mahendra Todi

Abhishek Dube

Deok-Kee Kim

Anita Madan

Gerd Pfeiffer

Bachir Dirahoui

Kriteshwar Kaur Kohli

Bong-Seok Suh

Naoyoshi Kusaba

Stephen G Fugardi

Dong-Hee Yu

Sean M Dillon

Kim Bosang

Kangguo Cheng

Carl John Radens

Oleg Gluschenkov

Ramachandra Divakaruni

Christian Lavoie

Mark R Visokay

Unoh Kwon

Joseph Francis Shepard, Jr

Karen A Nummy

Anthony Gene Domenicucci

Yong-Kuk Jeong

Claude Ortolland

Jin-Woo Choi

Rajeev Malik

Yoon-Hae Kim

Christopher N Collins

Jong-Ho Yang

Narasimhulu Kanike

Dong-Ick Lee

Edward R Engbrecht

Youngjin Choi

Dong Hee Yu

Bong-Seok Seo

Ali Babar Khan

The migration of dislocations into pristine single crystal material during crystal growth of an adjacent conductive strap is inhibited by a conductive barrier formed at the interface between the layers. The conductive barrier may be formed by implanting carbon impurities or depositing Si:C layer that inhibits dislocation movement across the barrier layer, or by forming a passivation layer by annealing in vacuum prior to deposition of amorphous Si to prevent polycrystalline nucleation at the surface of single crystalline Si, or by implanting nucleation promoting species to enhance the nucleation of polycrystalline Si away from single crystalline Si.

Method to improve crystalline regrowth

The present disclosure generally relates to semiconductor structures and, more particularly, to self-aligned nanotube structures and methods of manufacture. The structure includes at least one nanotube structure supported by a plurality of spacers and an insulator material between the spacers and contacting the at least one nanotube structure.

Self-aligned nanotube structures

A hard mask material is removed from an SOI substrate without using a chemical mechanical polish (CMP) process. A blocking material is deposited on a hard mask material after a deep trench reactive ion etch (RIE) process. The blocking material on top of the hard mask material is removed. A selective wet etching process is used to remove the hard mask material. Trench recess depth is effectively controlled.

Structure and method for hard mask removal on an SOI substrate without using CMP process

A method includes measuring a difference between a primary X-ray diffraction peak and a secondary X-ray diffraction peak, the primary X-ray diffraction peak corresponds to an unstrained portion of a semiconductor substrate and the secondary X-ray diffraction peak corresponds to a strained portion of the semiconductor substrate, the difference between the primary X-ray diffraction peak and the secondary X-ray diffraction peak includes a delta shift peak that corresponds to changes in a crystal lattice caused by a stress applied to the strained portion of the semiconductor substrate, the delta shift peak includes variations in a deep trench capacitance.

Capacitance monitoring using x-ray diffraction

Capacitance monitoring using X-ray diffraction

Embodiments of the present invention provide structures and methods for controlling stress in semiconductor wafers during fabrication. Features such as deep trenches (DTs) used in circuit elements such as trench capacitors impart stress on a wafer that is proportional to the surface area of the DTs. In embodiments, a corresponding pattern of dummy (non-functional) DTs is formed on the back side of the wafer to counteract the electrically functional DTs formed on the front side of a wafer. In some embodiments, the corresponding pattern on the back side is a mirror pattern that matches the functional (front side) pattern in size, placement, and number. By creating the minor pattern on both sides of the wafer, the stresses on the front and back of the wafer are in balance. This helps reduce topography issues such as warping that can cause problems during wafer fabrication.

Wafer stress control with backside patterning

An array or moat isolation structure for eDRAM with heterogeneous deep trench fill and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method further includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method further includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method further includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method further includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.

Array and moat isolation structures and method of manufacture

A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.

Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches

A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

Method of fabricating isolated capacitors and structure thereof

[object Object]

An array or moat isolation structure for eDRAM and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.

Growing community of inventors

Hopewell Junction, NY, United States of America

Oh-Jung Kwon