Advanced Micro Devices Corporation

Omnivision Technologies, Inc.

Ognjen Milic-Strkalj

Bruce Alan Gieseke

William McGee

Zoran Krivokapic

Emi Ishida

Carl Robert Huster

Concetta E Riccobene

Geoffrey Choh-Fei Yeap

Richard P Rouse

An image sensor includes a plurality of photodiodes disposed in a semiconductor material and a plurality of isolation structures disposed between individual photodiodes in the plurality of photodiodes. The plurality of isolation structures electrically isolate individual photodiodes in the plurality of photodiodes. A plurality of transistors are disposed proximate to the plurality of photodiodes and include a reset transistor, an amplifier transistor, and a row select transistor. An active region and a gate electrode of at least one transistor in the plurality of transistors are vertically aligned with an isolation structure in the plurality of isolation structures.

Method of fabricating fill factor enhancement for image sensor

Fill factor enhancement for image sensor

A memory system having a memory cell subject to read and write operations with shadow circuitry including a shadow cell configured to parallel operation of the memory cell. A wordline is connected to the memory cell and bitlines are connected to the memory cell and the shadow cell. Sense circuitry is connected to the bitlines for receiving data from the memory cell. An interlock cell is connected to the sense circuitry and the shadow cell to determine an occurrence of a non-redundant write operation, to provide the non-redundant write operation to the shadow cell, and to have the shadow cell prepare the bitlines for a read operation upon completion of the non-redundant write operation.

Semiconductor memory with shadow memory cell

A memory system, and method of operation therefor, is provided having memory cells for containing data, bitlines for writing data in and reading data from the memory cells, and wordlines connected to the memory cells for causing the bitlines to write data in the memory cells in response to wordline signals. A decoder is connected to the wordlines for receiving and decoding address information in response to a clock signal and an address signal to select a wordline for a write to a memory cell. Latch circuitry is connected to the decoder and the wordlines. The latch circuitry is responsive to the clock signal for providing the wordline signal to the selected wordline for the write to the memory cell and for removing the wordline signal from the selected wordline when the write to the memory cell is complete.

Wordline latching in semiconductor memories

A MOS semiconductor device is formed with reduced parasitic junction capacitance and reduced gate resistance. Embodiments include forming oxide sidewall spacers on side surfaces of openings in a nitride layer exposing the substrate, and performing a channel implant. A thin gate oxide layer is then thermally grown on the exposed portion of the substrate, and a relatively thin polysilicon layer is deposited on the gate oxide layer and the spacers. A metal layer, such as tungsten, is then deposited filling the opening, and planarized, as by chemical-mechanical polishing, using the nitride layer as a polish stop. Source/drain regions are thereafter formed by ion implantation, and the source/drain regions are silicided. The sidewall spacers and the nitride layer block the channel implant from the source/drain areas, thereby reducing parasitic junction capacitance, and the metal layer extending from above the gate oxide layer to the top of the gate reduces gate resistance, thereby increasing the switching speed of the finished device.

MOSFET with metal in gate for reduced gate resistance

A method is provided for directly measuring the source/drain resistance of a metal oxide semiconductor (MOS) device. Embodiments include partially deconstructing a typical MOS device by removing its gate and gate oxide from the substrate, as by etching, while preserving its gate sidewall spacer (typically silicon nitride). A sacrificial oxide spacer is formed on the nitride spacer, as by anisotropically etching a deposited oxide layer, and the area surrounding the sacrificial oxide spacer is filled with a layer of nitride. The sacrificial oxide spacer is then selectively etched to expose a portion of the main surface of the substrate and leave the nitride spacer and layer, thus creating a location near the edge of a source/drain region for a metal contact to be formed, as by chemical vapor deposition (CVD). The source/drain resistance of the device can then be directly and accurately measured by making electrical contact to the newly formed contact and a pre-existing source/drain contact on the same active area.

Formation of structure to accurately measure source/drain resistance

There is provided a MOS device with self-compensating threshold implant regions and a method of manufacturing the same which includes a semiconductor substrate, a partial first threshold implant forming a higher concentration layer, a gate oxide formed on the surface of the higher concentration layer, and a gate formed on a surface of the gate oxide. The MOS device further includes a second threshold implant for forming self-compensating implant regions in the substrate which is subsequently heated to define pockets. A third implant is performed to create lightly-doped source/drain regions. A sidewall spacer is formed on each side of the gate. A fourth implant is performed to create highly-doped source/drain regions between the lightly-doped source/drain regions and the pockets.

MOS device with self-compensating V.sub.aT -implants

The present invention provides a method for forming a MOS device having self-compensating threshold adjust implants and reduced junction capacitance. A semiconductor substrate of a first conductivity type is provided. A gate oxide is formed on the surface of the semiconductor substrate, and a polysilicon gate is formed on the surface of the gate oxide. A first implant of a dopant of the first conductivity type is performed so as to form self-compensating implant regions in the semiconductor substrate on opposite sides of the gate. Disposable sidewall spacers are then formed around the polysilicon gate. A second implant of a dopant of a second conductivity type is performed so as to create highly-doped source/drain regions which are self-aligned to the sidewall spacers. The substrate with self-compensating implant regions and the highly-doped source/drain regions is then subject to a rapid thermal anneal (RTA) process so as to activate the dopant in the self-compensating implant regions and the highly-doped source/drain regions. The dopant within the self-compensating regions diffuses laterally under the polysilicon gate to define pockets. Thereafter, the disposable sidewall spacers are removed. Finally, a third implant of a dopant of the second conductivity type is performed so as to create lightly-doped source/drain regions in the self-compensating implant regions on opposite sides of the gate.

Method for forming a MOS device with self-compensating V.sub.T -implants

A method of making a semiconductor device forms a gate on a substrate and provides a self-aligned diffusion source on the substrate, without the use of a mask. The diffusion source provides dopant material into the substrate. The self-aligning of the diffusion source avoids misalignment of the mask and improper doping. When the diffusion source is polysilicon or amorphous silicon, subsequent patterning and siliciding of the polysilicon forms silicided interconnect straps available for interconnecting devices on the semiconductor wafer.

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San Jose, CA, United States of America

Ognjen Milic-Strkalj