Advanced Micro Devices Corporation

Monolithic Power Systems, Inc.

Ognjen Milic

Zoran Krivokapic

Donald Ray Disney

Che-Hoo Ng

Michael Ren Hsing

Geoffrey Choh-Fei Yeap

Eric X Yang

Tiesheng Li

Jinghai Zhou

Martin E Garnett

Sunny Cherian

Kun Yi

A high-voltage transistor device comprises a spiral resistive field plate over a first well region between a drain region and a source region of the high-voltage transistor device, wherein the spiral resistive field plate is separated from the first well region by a first isolation layer, and is coupled between the drain region and the source region. The high-voltage transistor device further comprises a plurality of first field plates over the spiral resistive field plate with each first field plate covering one or more segments of the spiral resistive field plate, wherein the plurality of first field plates are isolated from the spiral resistive field plate by a first dielectric layer, and wherein the plurality of first field plates are isolated from each other, and a starting first field plate is connected to the source region.

High-voltage transistor device

The present disclosure discloses a lateral high-voltage transistor and associated method for making the same. The lateral high-voltage transistor comprises a semiconductor layer of a first conductivity type; a source region of a second conductivity type opposite to the first conductivity type in the semiconductor layer; a drain region of the second conductivity type in the semiconductor layer separated from the source region; a first isolation layer atop the semiconductor layer between the source region and the drain region; a first well region of the second conductivity type surrounding the drain region, extending towards the source region and separated from the source region; a second well region of the first conductivity type surrounding the source region; a gate positioned atop the first isolation layer above the second well region and an adjacent portion of the first well region; and a first buried layer of the first conductivity type under the first well region adjacent to the source region side of the lateral high-voltage transistor. A JFET is formed using the gate as a JFET top gate and the first buried layer as a JFET bottom gate.

Lateral high-voltage transistor and associated method for manufacturing

In one embodiment, a junction field effect transistor having a substrate, wherein formed on the substrate is a graded n-doped region having a high doping concentration in an inner region and a low doping concentration in an outer region, with a p-doped buried region adjacent to the graded n-doped region near the outer region, and a spiral resistor connected to the graded n-doped region at its inner region and at its outer region. An ohmic contact at the inner region provides the drain, an ohmic contact at the outer region provides the source, and an ohmic contact at the substrate provides the gate.

High voltage junction field effect transistor with spiral field plate

Voltage converters with integrated low power leaker device and associated methods are disclosed herein. In one embodiment, a voltage converter includes a switch configured to convert a first electrical signal into a second electrical signal different than the first electrical signal. The voltage converter also includes a controller operatively coupled to the switch and a leaker device electrically coupled to the controller. The controller is configured to control the on and off gates of the switch, and the leaker device is configured to deliver power to the controller. The leaker device and the switch are formed on a first semiconductor substrate, and the controller is formed on second semiconductor substrate separate from the first semiconductor substrate.

Voltage converters with integrated low power leaker device and associated methods

An input surge suppression device and method that uses a simple JFET structure. The JFET has its gate clamped to a predetermined value, its the drain receives the input voltage from an input power source, its source is connected to the input of a down-stream device, and a resistor connected between the drain and the gate or between the source and the gate. Thus, when the drain voltage approximates the clamped gate voltage, the source voltage nearly equals the drain voltage. When the drain voltage rises above the clamped gate voltage, the source voltage is lower than the drain voltage. The downstream device may be a DC-DC converter and the gate is biased by the enable (EN) pin of a DC-DC converter.

Input surge protection device using JFET

An integrated circuit CMOS structure and method for forming the structure provides gate sidewall spacers which are independently optimized for the n-channel and p-channel devices to improve hot-carrier lifetime while maintaining high drive currents. This is accomplished by providing polysilicon spacers for the n-channel devices and silicon nitride spacers for the p-channel devices.

Method and structure for improving hot carrier immunity for devices with very shallow junctions

A totally self-aligned transistor with a tungsten gate. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for these regions. A mid-gap electrode is also self-aligned to the transistor. The electrode is preferably formed from tungsten metal.

Totally self-aligned transistor with tungsten gate

An ultra-large scale integrated circuit semiconductor device having a laterally non-uniform channel doping profile is manufactured by using a Group IV element implant at an implant angle of between 0&deg; to 60&deg; from the vertical to create interstitials in a doped silicon substrate under the gate of the semiconductor device. After creation of the interstitials, a channel doping implantation is performed using a Group III or Group V element which is also implanted at an implant angle of between 0&deg; to 60&deg; from the vertical. A rapid thermal anneal is then used to drive the dopant laterally into the channel of the semiconductor device by transient enhanced diffusion.

Semiconductor with laterally non-uniform channel doping profile and manufacturing method therefor

An integrated semiconductor logic gate apparatus having optimized asymmetric channel regions and method for fabricating the apparatus is disclosed. The fabrication process includes ion-implanting the drain side of the channel to produce asymmetric channels on the gate transistors by using a criss-cross form of ion implantation. The criss-cross ion-implantation is performed after formation of the multiple gate stacks and is facilitated by a patterned photoresist mask that leaves an open, unprotected region above adjacent gate stacks through which the ion-implantation is performed. The criss-cross ion-implantation includes two tilt angles that are determined by tangent expressions that factor the height of the photoresist mask, the width of the unprotected opening over pairs of gate stacks and the width of the channel regions, including a distance relating to the point where the source/drain potential barrier is a minimum beneath the overlying gate stack. Adjacent gate stacks can have asymmetric channels with the same dopant concentration, or may be fabricated having different concentrations by varying the height of the photoresist mask to achieve a wider ion-implantation beam and thus form a higher dopant concentration on the target channel region. The optimized gates with higher dopant concentration improves off-state leakage current (10,amps/micron), but reduce the gate speed. The gates may also be optimized for gate speed and power consumption by producing uniformly doped asymmetric gates (20-50 pico-second fall time delays being achievable).

Optimization of logic gates with criss-cross implants to form asymmetric channel regions

An integrated circuit process technology for simultaneously forming multiple threshold voltage devices is disclosed. Devices having both high speed and low power consumption can be fabricated for use in integrated circuits having a need for both, such as microprocessors having cache memory.

Multiple threshold voltage semiconductor device fabrication technology

Semiconductor with laterally non-uniform channel doping profile

Channel doping is implemented such that dopants remain localized under the gate without migrating under the source/drain juctions during processing, thereby avoiding performance degradation of the finished device. Embodiments include implanting impurities at an acute angle to form a lateral channel implant localized below the gate after activation of source/drain regions, and activating the lateral channel implant by a low-temperature RTA during subsequent metal silicide formation. The use of a low-temperature RTA for electrical activation of the lateral channel implant avoids impurity migration under the source/drain junctions, thereby lowering parasitic junction capacitance and enabling the manufacture of semiconductor devices exhibiting higher circuit speeds with improved threshold voltage control.

Metal oxide semiconductor device with localized laterally doped channel

A totally self-aligned transistor with shallow trench isolation. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for these regions. Channel dopant deposited in the gate area is also self-aligned to the gate of the transistor.

Totally self-aligned transistor with polysilicon shallow trench isolation

An integrated semiconductor logic gate apparatus having optimized asymmetric channel regions and method for fabricating the apparatus is disclosed. The fabrication process includes ion-implanting the drain side of the channel to produce asymmetric channels on the gate transistors by using a criss-cross form of ion implantation. The criss-cross ion-implantation is performed after formation of the multiple gate stacks and is facilitated by a patterned photoresist mask that leaves an open, unprotected region above adjacent gate stacks through which the ion-implantation is performed. The criss-cross ion-implantation includes two tilt angles that are determined by tangent expressions that factor the height of the photoresist mask, the width of the unprotected opening over pairs of gate stacks and the width of the channel regions, including a distance relating to the point where the source/drain potential barrier is a minimum beneath the overlying gate stack. Adjacent gate stacks can have asymmetric channels with the same dopant concentration, or may be fabricated having different concentrations by varying the height of the photoresist mask to achieve a wider ion-implantation beam and thus form a higher dopant concentration on the target channel region. The optimized gates with higher dopant concentration improves off-state leakage current (10.sup.-8 amps/micron), but reduce the gate speed. The gates may also be optimized for gate speed and power consumption by producing uniformly doped asymmetric gates (20-50 pico-second fall time delays being achievable).

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San Jose, CA, United States of America

Ognjen Milic