Pmc-sierra, Inc.

Glenayre Electronics, Inc.

Other

Pmc-sierra Us, Inc.

Ognjen B Katic

Claudio Gustavo Rey

William Dean Warner

Paul V Yee

Anthony Eugene Zortea

William Michael Lye

Stephen Bates

Jurgen Hissen

Jatinder Chana

John Philip Plasterer

Marlo Rene Gothe

Mathew McAdam

William D Warner

Nino Pietro Ferrario

Jonathan Robert Gay

Terence K W Lau

A method for evaluating operation of a receiver comprising an analog front end, a plurality of samplers connected in parallel to the analog front end, the plurality of samplers comprising a plurality of utility samplers, a plurality of data samplers and a plurality of timing samplers, an unrolled decision feedback equalizer (UDFE) connected to outputs of the plurality of data samplers, and a serial input parallel out (SIPO) block connected to an output of the UDFE and outputs of the plurality of utility and timing samplers. The method comprises adjusting settings of the plurality of utility samplers to sweep across a range of interest, at each of a plurality of points comparing a selected output of one of the plurality of utility samplers at that point to an output of one of the plurality of data samplers to detect an error event, and, accumulating the error events.

On-chip bathtub BER measurement for high-speed serdes diagnostics

A method is disclosed for setting or modifying a threshold voltage in a NAND flash memory, using an optimization method and based on an error, such as stored in a threshold voltage table. In an embodiment, a method is provided to optimize the read voltage on a NAND flash memory in order to minimize the errors on the NAND flash memory in the fewest reads operations as possible. Advantageously, the method of the present disclosure is more reliability as the method minimizes a Raw Bit Error Rate (RBER) on the NAND flash memory. In an embodiment, a NAND controller adjusts an existing cell read threshold voltage for a selected cell, using an iterative optimization method, based on a difference between first and second error rates, or a difference between first and second probabilities, to generate an adjusted cell read threshold voltage.

Threshold voltage adjustment in solid state memory

Apparatus and methods mitigate a problem of equalizing communications signals that have been distorted by severe non-linearities such as clipping or harsh compression. For example, severe non-linearity occurs when signal compression or signal clipping occurs at rates above 20% of the data transmission interval. Severe non-linearities may significantly reduce system performance. Disclosed techniques selectively apply DSP equalization based on the detection of non-linearity for a present sample or one or more samples prior to the present sample. These techniques can be implemented in relatively low-cost high-speed SerDes designs to improve eye openings and reduce sensitivity to InterSymbol Interference (ISI) and to improve bit error rate (BER).

Equalizer for heavily clipped or compressed communications signals

Apparatus and methods generate equalizer coefficients for an equalizer of a receiver. In a high-speed receiver, received symbols can be subject to inter-symbol-interference (ISI). An equalizer can compensate for ISI and improve a bit error rate (BER). However, traditional adaptive techniques to generate coefficients for equalization can generate corrupted coefficients when equalized samples used for adaptation are based on clipped or heavily compressed signals. In certain situations, the clipping rate can be relatively high, such as over 20%. Equalizer performance is improved when the equalized symbols used directly or indirectly for adaptation are selected such that equalized symbols based on clipped input samples are not used for adaptation.

Equalizer adaptation for heavily compressed or clipped communications signals

Disclosed is a technique for mitigating the effect of an in-band interferer in Orthogonal Frequency Division Multiplexing (OFDM) wireless or wired networks that employ soft decision Viterbi decoder in the physical layer. The technique uses an independent estimation of the signal quality, which is passed to the Viterbi algorithm decoder so that it is able to discard the corrupted subcarriers. This improves the error correction capability of the Viterbi algorithm decoder in a receiver, which leads to fewer retransmissions and into higher information throughput.

Interference erasure using soft decision weighting of the Viterbi decoder input in OFDM systems

A decision feedback equalizer (DFE) for a receiver that can reduce jitter is disclosed. The DFE uses an equalizer structure that employs a symbol sampling operation at a decision device, also known as a slicer. In a receiver, the phase of a signal, such as an equalized signal, is typically estimated from zero crossings in the clock recovery operation. Fluctuations in these zero crossings makes phase of the reproduced clock unstable, which decreases error performance in an associated receiver. Embodiments advantageously align inter-symbol interference (ISI) canceling terms from a feedback filter (FBF) relatively well, and thereby provide equalization of a relatively large portion of a symbol period. This advantageously stabilizes the phase of an equalized signal and reduces jitter.

Decision feedback equalizer (DFE) for jitter reduction

Methods and apparatus for canceling pre-cursor inter-symbol interference (ISI) are disclosed. In a digital communication system, a significant amount of noise can be attributed to the pre-cursor portion of the ISI. In a receiver, it can be relatively difficult to compensate for pre-cursor ISI in part because pre-cursor ISI is a result of one or more symbols that have yet to arrive at the receiver. One embodiment removes a portion of this ISI by using multiple detection thresholds in parallel. For example, data slicing (generation of a hard decision) can include three thresholds. These thresholds for slicing include a positive offset, a negative offset and no offset. The positive and negative offsets can correspond to the expected pre-cursor component of the data channel for which the data is transmitted or to a fraction thereof. The path with the correctly-compensated ISI is selected later.

Pre-cursor inter-symbol interference cancellation

An equalizer for return-to-zero (RZ) signals comprises: (a) an equalizer core for equalizing the received signal; (b) a decision corrector for detecting and correcting misplaced pulses and double pulses in the equalized signal using known characteristics and properties of the RZ signal itself; and (c) an error calculator that generates an error signal for updating tap values based on the initial outputs of the equalizer core and the corrected outputs of the decision corrector. The decision corrector comprises a zero assertion counter that generates a clock synchronized with the timing of the received signal, and corrects the equalized signal by forcing zeroes in those portions of the equalized signal that the synchronized clock indicates should be 'RZ' zeroes (as opposed to 'data' zeroes or &#x201c;data&#x201d; symbols &#x201c;1&#x201d; or &#x201c;&#x2212;1&#x201d;). The decision corrector further comprises a misplaced pulse detector for detecting misplaced pulses and double pulses based on both the output of the zero assertion counter and coding in the RZ signal, and corrects the equalized signal by moving the misplaced pulse or doubled portion of the pulse forward or backward in time in accordance with the principles of the RZ coding scheme used. The equalizer can further comprise interpolators for generating a plurality of signals based on the equalized signal, to provide a greater diversity of information for the decision corrector.

Equalizer and equalization method for return-to-zero signals

An apparatus and method for jointly equalizing a return to zero (RZ) signal and detecting timing errors in the RZ signal, using values or indices from equalizer taps, including a set reference tap that does not shift. A timing error detector detects a timing error based on a group delay measured from the equalizer tap information, and then adjustment circuitry modifies samples of the received RZ signal prior to their equalization to offset that timing error. Methods of modifying the samples to offset the timing error include adjusting the timing of the sampler, or adjusting the sampled data using intermediate, interpolated samples generated by a timing interpolation filter.

Joint equalization and timing acquisition for RZ signals

A physical channel estimator for a communication system using pilot symbols and an equalizer uses a model of the system in which the impulse response of the physical channel is considered separately from the impulse responses of the pulse shaping filters in the transmitter and receiver of the communication system. The system is modeled as if the signals were propagated first through both pulse shaping filters and then through the physical channel. To estimate the physical channel impulse response, known pilot symbols are transmitted and then sampled. The pilot symbol samples and the known impulse responses of the pulse shaping filters are then used to estimate the physical channel impulse response. In one embodiment, the physical channel impulse response is considered time-invariant over the estimation period and a sufficient number of pilot symbol samples are taken so that the system is overdetermined. A least squares method is then used to estimate the physical channel impulse response from the pilot symbol samples and the known responses of the pulse shaping filters. Further refinements include conditioning the estimated physical channel impulse response to improve performance in low SNR conditions and estimating a DC offset incurred from demodulating the received signal.

Physical channel estimator

An interpolator having a linear phase response has a first stage implemented with an IIR filter to achieve the narrow transition bandwidth with relatively few filter coefficients. Zero-stuffing and filtering are used to achieve the interpolation. A forward-backward filtering methodology is then used to achieve a linear phase response for the IIR filter. The input sequence to be interpolated is zero stuffed and passed through the IIR filter a first time. Then the time order of the resulting sequence is reversed and then passed through the IIR filter a second time. After that, the resulting output sequence is reversed again. Guard blocks are added to both ends of the input sequence, and then a block of zeros is appended to the zero-stuffed guarded input sequence. The appended zero block causes the startup and ending transient effect of the IIR filter's step response to be equal at both ends, which tends to improve the accuracy of the interpolation. Subsequent zero-stuffing and filtering by FIR filter stages are used to further increase the interpolation. A linear interpolator may also be included after the FIR filter stages.

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Vancouver, Canada

Ognjen B Katic