Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Yissum Research Development Company of the Hebrew University of Jerusalem Ltd.

Ofir Pele

Alexander Bazarsky

Ran Zamir

Ariel Navon

Stella Achtenberg

Karin Inbar

Omer Fainzilber

Daniel Joseph Linnen

Tomer Tzvi Eliash

Rami Rom

Eran Sharon

Shay Benisty

Yehuda Hahn

Dudy David Avraham

Alon Marcu

Chun Sei Tsai

Alex Bazarsky

Michael Werman

Aimamorn Suvichakorn

Jonathan Lloyd

Amit Chattopadhyay

Anand Gupta

Krzysztof Gladysz

Kameron Jung

Tommer Kuper Lotan

Methods are provided for tactically deploying machine learning operations within existing storage devices without the need for additional capital investment. Machine learning operations are specifically designed to locate and evaluate multiple types of data to complete an operation, including synthesizing missing data. These operations may be processed within a SoC of a storage device as embedded software. Storage devices designed to utilize machine learning methods within existing configurations can include a non-volatile memory for storing data, executable instructions, and a processor to conduct a variety of steps. The steps can include executing a plurality of applications stored in the non-volatile memory, and receiving a request for data, including measurements, from at least one of the applications. The steps can further determine if the requested data is suitable for substitution by an inference and subsequently select at least one machine learning model for generating a suitable inference.

Embedded multi-attribute machine learning for storage devices

Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may be a Neural Turing Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, an NTM controller sets the size of the NTM matrix based on a storage access granularity of the NVM array. For instance, if the NVM reads and writes data in flash memory unit (FMUs), the NTM controller sets the size of the NTM matrix to correspond to the size of an integer number of FMUs. In some examples, the NVM array includes on-chip NTM circuitry configured to perform at least some NTM read head and write head operations. Threshold-based processing is described that can reduce an amount of NTM data read from the NVM array. In other examples, volatile memory is employed rather than an NVM array.

Systems and methods for use with recurrent neural networks

Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

Non-volatile memory die with deep learning neural network

Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.

Memory (NVM) devices for use with recurrent neural networks

The present disclosure generally relates to data storage devices, such as solid state drives. A data storage device includes a controller, one or more volatile memory locations, and one or more non-volatile memory locations. Computations, including reinforcement learning algorithms, may be completed by the controller using the one or more non-volatile memory locations. Data associated with reinforcement learning is stored in a table on one or more planes of the non-volatile memory, where the results from the computations update the table with the relevant values. The data in the table are aligned to one or more wordlines, such that sensing the wordline senses all the data stored in the table.

Memory device with reinforcement learning with Q-learning acceleration

Hybrid memory management of non-volatile memory (NVM) devices for use with recurrent neural networks

Advanced ultra-low power error correcting codes are generated using soft quantization and lattice interpolation based on clock and Syndrome Weight. Reinforcement learning may be used to generate threshold values for flipping bits for low density parity check Ultra-Low Power error correction codes. The threshold values can be generated offline and downloaded to a storage device or generated while the storage device is in use.

Advanced ultra low power error correcting code encoders and decoders

A method and apparatus for video processing on a data storage device. A chip bound architecture includes a CMOS coupled to one or more NAND die, the CMOS including one or more processors, memories, and error correction code (ECC) engines capable of processing video data. According to certain embodiments, macroblocks are correlated between two I-frames, including motion vectors to define different locations of correlated macroblocks. A P-frame may be determined from a previous I-frame and its correlated macroblocks and motion vectors, while a B-frame may be determined from two or more adjacent I-frames with concomitant macroblocks and motion vectors, as well as P-frames associated with an adjacent I-frame.

Video processing in a data storage device

A method of temperature compensation to read a flash memory device includes determining a state of the flash memory device. An action is selected with a maximum Q-value from a Q-table for the current state during exploitation. A read operation of a code word from the flash memory device is conducted using one or more parameters according to the selected action. The code word is decoded with an error correction code (ECC) process.

Machine learning for temperature compensation

Disclosed herein are memory devices, systems, and methods of encoding and decoding data. In one aspect, an encoded data chunk is received and segmented into data segments with similar features. Each segment can be decoded based on its features. Data can also be rearranged and partitioned so as to minimize an entropy score that is based on the size and entropy of the data partitions. The approach is capable of enhancing performance, reducing decoding latency, and reducing power consumption.

Memory device with enhanced error correction via data rearrangement, data partitioning, and content aware decoding

Various method and apparatus embodiments for data dependent error correction code (ECC) encoding are disclosed. In one embodiment, a data object may include multiple portions, with each portion having different characteristics. An ECC encoder may allocate error correction resources (e.g., parity bits) to the different portions at respectively different data rates (e.g., more error correction resources to some portions relative to other portions). Upon completion of the allocation, the data object and the associated error correction resources are forwarded to a storage medium for storage therein.

Data dependent allocation of error correction resources

A method of determining whether two patterns having a plurality of homologous regions match, comprising: generating a set of decisions associated with values (k,n) for determining whether the patterns match, where k, is a number of non similar homologous regions from a sample of size, n, of the homologous regions; constraining the decisions so that a probability of providing a false negative decision that there is no match when in fact there is a match is less than or equal to a predetermined upper bound; configuring the association of decisions and pairs (k,n) to minimize running time of a computer programmed to use the set of decisions to determine whether there is a match; and using a computer programmed with the set of decisions to determine if the patterns match.

Growing community of inventors

Hod Hasharon, Israel

Ofir Pele