Densbits Technologies Ltd.

Ofir Avraham Kanter

Hanan Weingarten

Avi Steiner

Erez Sabbag

Michael Katz

Eli Sterin

Avigdor Segal

Ilan Bar

A system and method for unbiased rounding away from, or toward, zero by truncating N bits from a M bit input number to provide a M&#x2212;N bit number, and adding the equivalent value of '&#xbd;' to the M&#x2212;N bit number unless the input number is negative, or positive, respectively, and the N truncated bits represent exactly &#xbd;. The method for rounding away from zero may include outputting a (M&#x2212;N) bit truncated number if the M-bit input number is negative and the sequence of N truncated bits comprises a most significant bit of 1, followed by zeros; and otherwise, computing and outputting a sum of (a) a number that has an equivalent value of one followed by (N&#x2212;1) replicas of zero, the one provided by applying a logical operation on the most significant bit of the sequence of truncated bits and (b) the (M&#x2212;N) bit truncated number.

Apparatus and methods for hardware-efficient unbiased rounding

A decoder, an encoder, a decoding method and an encoding method are provided. The encoding method includes receiving data; generating a set of first codewords by applying a first encoding process on the received data; and performing a second encoding process on a folded version of each first codeword to provide a set of second codewords, wherein a folded version of a first codeword is representative of a storage of the first codeword in a two dimensional memory space, wherein the second codeword comprises redundancy bits.

Encoding method and system, decoding method and system

A low power Chien searching method employing Chien search circuitry comprising at least two hardware components that compute at least two corresponding bits comprising a Chien search output, the method comprising activating only a subset of the hardware components thereby to compute only a subset of the bits of the Chien search output; and activating hardware components other than those in the subset of hardware components, to compute additional bits of the Chien search output other than the bits in the subset of bits, only if a criterion on the subset of the bits of the Chien search output is satisfied.

Low power chien-search based BCH/RS decoding system for flash memory, mobile communications devices and other applications

A system and method are provided for data recovery in a multi-level cell memory device. One or more bits may be programmed sequentially in one or more respective levels of multi-level cells in the memory device. An interruption of programming a subsequent bit in a subsequent second or greater level of the multi-level cells may be detected. Data may be recovered from the multi-level cells defining the one or more bits programmed preceding the programming interruption of the second or greater level.

System and method for data recovery in multi-level cell memories

A method and an apparatus that has Chien search capabilities, the apparatus includes a first hardware circuit and a second hardware circuit. The first hardware circuit evaluates an error locator polynomial for a first element of a finite field over which the error locator polynomial is defined to provide a first set of intermediate results and a first Chien search result and provides the first set of intermediate results to the second hardware circuit; the second hardware circuit evaluates the error locator polynomial for a second element of the finite field to provide a second Chien search result in response to the first set of intermediate results. The first hardware circuit may be substantially bigger than the second hardware circuit and the first element may differ from the second element.

Compact chien-search based decoding apparatus and method

Chien search apparatus operative to evaluate an error locator polynomial having a known rank and including a sequence of terms for each element in a finite field whose elements correspond respectively to bits in each of a stream of data blocks to be decoded, the apparatus comprising a sequence of functional units each operative to compute a corresponding term in the sequence of terms included in the error locator polynomial, each term having a degree; and a power saving unit operative to de-activate at least one individual functional unit from among the sequence of functional units, the individual functional unit being operative, when active, to compute a term whose degree exceeds the rank.

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Yoqneam, Israel

Ofir Avraham Kanter