Sandisk Technologies Inc.

Ofer Shapira

Eran Sharon

Idan Alrod

Ariel Navon

Yehuda Hahn

Alexander Bazarsky

Alex Bazarsky

Opher Lieber

Alon Eyal

Danny Berler

Yonatan Karlik

Idan Alord

A memory system is configured to perform a test operation to determine a deviation of a target storage location's bit error rate response relative to a model. The memory system determines the deviation level by measuring data sets stored in the target storage location to determine an actual bit error rate value and another actual parameter value used to estimate bit error rate. The memory system obtains an estimated value from the model based on the actual values and identifies the deviation by comparing the estimated value with the actual values.

BER model evaluation

Data is programmed in a respective block of non-volatile three dimensional memory. The block contains a plurality of rows of subblocks, each row having S subblocks. Programming data in the respective block includes successively programming data in individual rows of the respective block. Programming data in each row is completed prior to programming data in a next row. Programming data in a row includes successively programming data in individual subblocks of the row, in a predefined order. The programming of data in each subblock is completed prior to programming data in a next subblock. While programming data in each individual subblock, a number of XOR signatures, sufficient in number to enable recovery from a short circuit that disables two or three word lines, are generated in volatile memory, and then copied to non-volatile memory prior to programming data in a next subblock in the respective block.

Data recovery in three dimensional non-volatile memory array after word line short

A storage system and method for providing gray levels of read security are provided. In one embodiment, a storage system is provided comprising a memory and a controller in communication with the memory. The controller is configured to perform a test of a security feature of the storage system; and in response to failure of the test of the security feature of the storage system, degrade a subsequent read of a set of locations in the memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Storage system and method for providing gray levels of read security

A method performed by a controller includes initiating a first data write operation and an erase operation on a portion of a non-volatile memory. The first data write operation corresponds to a first write resolution. The method includes initiating a second data write operation to write test data to the portion of the non-volatile memory. The second data write operation corresponds to a second write resolution that is greater than the first write resolution. The method also includes reading a representation of the test data from the portion of the non-volatile memory.

Burn-in memory testing

A device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to determine a first shaping level corresponding to applying a first shaping operation to data to be stored to the non-volatile memory. The controller is further configured to, in response to the first shaping level exceeding a threshold, perform a second shaping operation to generate shaped data that corresponds to the data, the shaped data having a second shaping level that is less than the threshold.

Constrained data shaping

A memory is released for use without pre-verification of its memory blocks as being defect free. Some memory blocks are subjected to a verification process when the computer memory is in use in order to verify a minimum number of memory blocks required for high performance program operation as being defect free. The verification process continues as the computer memory is in use in order to maintain the minimum number of memory blocks required for high performance operation in the verified defect free state. A verification mode of either no verification, delayed verification, or immediate verification is applied to memory blocks used for regular performance program operation. Delayed verification is maintained until an ability to recover the stored data is going to be lost. Immediate verification can be performed using bit error rate analysis. Some verification processes are performed using aggressive programming trim and/or multiple word line sensing for faster programming.

Selective online burn-in with adaptive and delayed verification methods for memory

Systems and methods for performing defect detection and data recovery within a memory system are disclosed. A controller of a memory system writes data to a physical location of a memory and stores the physical location of the memory in a Flash Management Unit Tag cache ('Tag cache'). The controller identifies a data keep cache that is associated with the physical location of memory and updates an XOR sum stored in the identified data keep cache. The controller determines whether to perform a verification operation, and in response to a determination to perform the verification operation, verifies data stored at each physical location that has been stored in the Tag cache since a previous verification operation. Additionally, the controller determines whether to perform a reset operation, and in response to a determination to perform the reset operation, flushes the Tag cache and the plurality of data keep caches.

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Herzliya, Israel

Ofer Shapira