Intel Corporation

Ofer Nathan

Ankush Varma

Alexander Gendler

David Hunt

Adwait Purandare

Suresh Chemudupati

Pritesh P Shah

Christopher M Macnamara

A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.

Hardware-assisted core frequency and voltage scaling in a poll mode idle loop

Growing community of inventors

Haifa, Israel

Ofer Nathan