Amazon Technologies, Inc.

Nxp USA, Inc.

Ofer Naaman

Adi Habusha

Nafea Bshara

Erez Izenberg

Tzachi Zidenberg

Ali Ghassan Saidi

Itai Avron

Itamar Bonne

Michael Zuzovski

Nir Bar-Or

Osnat Katz

Uri Leder

Michael Zarubinsky

Benny Pollak

Shlomo Beer-Gingold

Sergey Kleyman

Max Chvalevsky

Ohad Gdalyahu

Simaan Bahouth

Leonid Froenchenko

Lior Podorowski

Aviv Bakal

Systems and methods are provided to generate time data according to a nominal frequency and based on an available frequency. A hardware clock of the system can operate according to the available frequency. The system can identify a difference between the available frequency and a nominal frequency. Based on the difference, the system can generate time data according to the nominal frequency. To generate the time data, for each clock cycle of a plurality of clock cycles according to the available frequency, the system can determine whether to increment or maintain a value of the time data for a prior clock cycle of the plurality of clock cycles. The system can perform one or more functions based on the time data.

Configurable system counter based on a hardware clock frequency

The coherency of data can be maintained even for accelerators that may not directly support, or be part of, a coherency protocol or domain. A pair of agents can be utilized that include an application accelerator agent and a coherent agent. The coherent agent can support the coherency protocol and track coherency information for data in the coherency environment, to ensure coherent access to the data. The application accelerator agent can work with the coherent agent to obtain the data according to the coherency protocol, then perform operations on the data corresponding to a respective application or process. Such an approach enables an accelerator to function like a processor or processor core that otherwise supports the coherency protocol and is part of the coherency domain. A single coherent agent can be used to maintain coherency information for multiple other components or agents.

Coherent agents for memory access

A packet processing technique can include receiving a packet, and parsing the packet based on a protocol field to generate a parse result vector. The parse result vector is used to select between forwarding the packet to a virtual machine executing on a host processing integrated circuit, forwarding the packet to a physical media access controller, multicasting the packet to multiple virtual machines executing on the host processing integrated circuit, and sending the packet to a hypervisor.

Configurable parser and a method for parsing information units

A system includes an obsolete cache-line vector having a plurality of memory elements, wherein each memory element has a one-to-one correspondence to a cache line entry of a cache memory. The vector can capture cache line errors that occur at different times from an error detection logic associated with the cache memory. A counter can be coupled to the obsolete cache-line vector for tracking how many of the memory elements in the vector are activated. When a predetermined threshold is reached, a threshold comparator can release a trigger for further analysis. An error events logger can be used to track all of the errors that occurred. The error events logger can also use a time stamp, which can assist the RAS system in analyzing a correlation between the errors, such as patterns that occur and time differences between the errors.

Cache memory error analysis and management thereof

An interposer circuit is used between an interrupt controller and a processor core to facilitate direct injection of a virtual interrupt into a guest executing on the processor core, even though the interrupt controller does not support the direct injection. The interposer circuit can convert a command received from the interrupt controller for a physical interrupt into another command for a virtual interrupt to make the processor core believe that the processor core has received a virtual interrupt even though the interrupt controller is not able to provide the virtual interrupt. The virtual interrupt can be directly injected into the processor core without the intervention of a hypervisor executing on the processor core.

Direct injection of a virtual interrupt

A system captures errors and stores an obsolete line bit qualifier per cache entry that can be used to dynamically mark a specific cache entry as obsolete. For example, the cache entry can be marked as obsolete after detecting repetitive single-bit errors on a same cache entry within a predetermined period of time. For cache lines marked as obsolete, a cache controller can ensure that the cache line entry remains unused. The detection of a repetitive single-bit error can be accomplished by implementing a counter per cache entry and a timer. The counter counts errors within a timer window, and a repetitive error is reported if the counter reaches a threshold level. By catching repetitive single-bit errors before such errors spread to multi-bit errors, the system can increase the life span of the server computer.

Increasing of cache reliability lifetime through dynamic invalidation and deactivation of problematic cache lines

Techniques are disclosed for transferring a message between a sender agent and a receiver agent via a shared memory having a main memory and a cache. Feedback data indicative of a number of read messages in the shared memory is generated by the receiver agent. The feedback data is sent from the receiver agent to the sender agent. A number of unread messages in the shared memory is estimated by the sender agent based on the number of read messages. A threshold for implementing a caching policy is set by the sender agent based on the feedback data. The message is designated as cacheable if the number of unread messages is less than the threshold and as non-cacheable if the number of unread messages is greater than the threshold. The message is written to the shared memory based on the designation.

Configurable caching policy for transferring data via shared memory

Techniques to prioritize serially transmitted data are described. The sequence of serial data segments being transmitted across a communication interface is modified such that prioritized segments that may require a higher refresh rate are transmitted more frequently than regular data segments. A prioritization configuration register can be implemented in both the transmitter and the receiver such that both sides are programmed with the altered sequence of transmission. The prioritization configuration stored in the prioritization configuration register can indicate the points in the sequence where the out-of-order transmission occurs, and which data segments are transmitted in them. The transmitter can use this information to serialize the data segments according to the prioritization, and the receiver can re-parallelize the received data as indicated by the altered sequence.

Prioritized parallel to serial interface

A packet processing technique can include selecting a protocol field from the packet, and performing a comparison of the selected protocol field with comparison data in a compare logic array to output a protocol index. The protocol index can be used as an address to read parsing commands from a parse control table, and a parse result can be generated based on executing the parsing commands on the packet. The parse results are used to derive a parse result vector, which can be used by a forwarding engine to forward the packet.

In various implementations, provided are systems and methods for an integrated circuit including a completer device, a requester device, and an interconnect fabric. The requester device is configured to generate transactions to the completer device, where each transaction includes a request packet that includes an attribute associated with the completer device; and the interconnect fabric is coupled to the requester device and the completer device. The integrated circuit can also include a QoS regulator configured to identify, based on a first attribute associated with the completer device, a first QoS value establishing a first priority level for a first request packet generated by the requester device, and modify the first request packet to include the first QoS value.

Interconnect address based QoS regulation

A system, comprising: a configurable parser that comprises one or more configurable parsing engines, wherein the configurable parser is arranged to receive a packet and to extract from the packet headers associated with a set of protocols that comprises at least one protocol; a packet type detection unit that is arranged to determine a type of the packet in response to the set of protocols; and a configurable data integrity unit that comprises a configuration unit and at least one configurable data integrity engine; wherein the configuration unit is arranged to configure the at least one configurable data integrity engine according to the set of protocols; and wherein the at least one configurable data integrity engine is arranged to perform data integrity processing of the packet to provide at least one data integrity result.

Generic data integrity check

Interactive compilation of software to a hardware language may be performed to satisfy formal verification constraints. Source code for software to be executed on a hardware design may be received. Intermediate code may be generated from the source code as part of translating the source code to a hardware language used to specify the hardware design. The intermediate code may be provided via an interface and updates to the intermediate code may be received. The updated source code may then be used to complete translation of the source code to the hardware language.

Growing community of inventors

Hod-Hasharon, Israel

Ofer Naaman