Intel Corporation

Compugen Ltd. Corporation

Bayer Aktiengesellschaft

Mcafee, Inc.

Bayer Pharma Aktiengesellschaft

Ofer Levy

Amir Toporik

Zeev Sperber

Ahmad Yasin

Zurit Levine

Jason W Brandt

Liat Dassa

Amit Novik

Sergey Nemzer

Yossef Kliger

Zohar Tiran

Tsvika Kurts

Beeman C Strong

Michael W Chynoweth

Shira Walach

Galit Rotman

Eve Montia

Yaron Kinar

Merav Beiman

Marina Bubis

Anat Cohen-Dayag

Avi Yeshah Rosenberg

Tania Pergam

Cynthia Koifman

Dalit Landesman-Milo

Itamar Borukhov

Anat Amir

Michael Mishaeli

Spencer Liang

Ilan Vaknin

Itamar S Kazachinsky

Gabi Malka

Assaf Wool

Ehud Schreiber

Ravi L Sahita

Matthew C Merten

Stanislav Shwartsman

Mark Leslie White

Gad S Cojocaru

Shirley Sameah-Greenwald

Rajshree Chabukswar

Peter Lachner

Yuriy Bulygin

Christopher Chan

Sandeep Kumar

Peggy J Irelan

Lance Stapleton

Andrew W Drake

Yosi Gozlan

Angela D Schmid

Grant G Zhou

Anat Oren

Arthur Machlenkin

Yair Benita

Shirley Sameach- Greenwald

John M Esper

Emile Ziedan

Shirley Sameach-Greenwald

Robert Valentine

Vedvyas Shanbhogue

Barry E Huntley

Krishnakanth Venkata Sistla

Michael Lemay

Alexander Gendler

Ron Gabor

Konrad K Lai

Ravi Rajwar

Lihu Rappoport

Shlomo Raikin

Igor Yanover

Gideon Gerzon

Xiaoning Li

Adi Yoaz

Jonathan D Combs

Ido Ouziel

Frank Binns

John J Hunter

Andreas Kleen

Hisham Shafi

Ernest Knoll

Uwe Gritzan

Tong Li

Ofer J Nathan

Ariel Szapiro

Mayank Bomb

Lars Röse

Gal Ofir

Lev Makovsky

Andrew A Furtak

Guy Patkin

Iris Hecht

Ariel Sabba

Oleksandr Bazhaniuk

Shani Rehana

Thomas F Toll

Md Asifur Rahman

Thilo Schmitt

Charlie J Hewett

Christopher Mark Chrulski

Rafi Marom

The present invention is directed to PVRIG polypeptides and their uses.

PVRIG polypeptides and methods of treatment

The present invention relates to a novel pharmaceutical combination comprising an ILDR2 antagonist according to any of the aforementioned claims, plus one or more other therapeutically active compounds, and to novel specific ILDR2 antagonists.

ILDR2 antagonists and combinations thereof

A processor includes a front end including circuitry to decode an instruction from an instruction stream and a core including circuitry to process the instruction. The core includes an execution pipeline, a dynamic core frequency logic unit, and a counter compensation logic unit. The execution pipeline includes circuitry to execute the instruction. The dynamic core frequency logic unit includes circuitry to squash a clock of the core to reduce a core frequency. The clock may not be visible to software. The counter compensation logic unit includes circuitry to adjust a performance counter increment associated with a performance counter based on at least the dynamic core frequency logic unit circuitry to squash a clock of the core to reduce a core frequency.

Method and logic for maintaining performance counters with dynamic frequencies

An example processor that includes a decoder, an execution circuit, a counter, and a last branch recorder (LBR) register. The decoder may decode a branch instruction for a program. The execution circuit may be coupled to the decoder, where the execution circuit may execute the branch instruction. The counter may be coupled to the execution circuit, where the counter may store a cycle count. The LBR register coupled to the execution circuit, where the LBR register may include a counter field to store a first value of the counter when the branch instruction is executed and a type field to store type information indicating a type of the branch instruction.

Branch type logging in last branch registers

A processor of an aspect includes a decode unit to decode a thread pause instruction from a first thread. A back-end portion of the processor is coupled with the decode unit. The back-end portion of the processor, in response to the thread pause instruction, is to pause processing of subsequent instructions of the first thread for execution. The subsequent instructions occur after the thread pause instruction in program order. The back-end portion, in response to the thread pause instruction, is also to keep at least a majority of the back-end portion of the processor, empty of instructions of the first thread, except for the thread pause instruction, for a predetermined period of time. The majority may include a plurality of execution units and an instruction queue unit.

Thread pause processors, methods, systems, and instructions

In an embodiment, a processor for Return Oriented Programming (ROP) detection includes at least one execution unit; a plurality of event counters, each event counter associated with a unique type of a plurality of types of control transfer events; and a ROP detection unit. The ROP detection unit may be to: adjust a first event counter in response to detection of a first type of control transfer events; in response to a determination that the first event counter exceeds a first threshold, access a first configuration register associated with the first event counter to read configuration data; identify a set of ROP heuristic checks based on the configuration data read from the first configuration register; and perform each ROP heuristic check of the identified set of ROP heuristic checks. Other embodiments are described and claimed.

Detection of return oriented programming attacks in a processor

In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.

Tracking mode of a processing device in instruction tracing systems

Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.

Scatter using index array and finite state machine

This invention relates to a novel target for production of immune and non-immune based therapeutics and for disease diagnosis. More particularly, the invention provides therapeutic antibodies against VSIG1, ILDR1, LOC253012, AI216611, C1ORF32 or FXYD3 antigens, which are predicted co-stimulatory family members and which are differentially expressed in cancers including, lung cancer, ovarian cancer, and colon cancer, and diagnostic and therapeutic usages. The use of these antibodies for modulating B7 costimulation and related therapies such as the treatment of autoimmunity are also provided. This invention further relates to the discovery of extracellular domains of VSIG1 and its variants, FXYD3 and its variants, ILDR1 and its variants, LOC253012 and its variants, AI216611 and its variants, and C1ORF32 and its variants awhich are suitable targets for immunotherapy, cancer therapy, and drug development.

Polypeptides and polynucleotides, and uses thereof as a drug target for producing drugs and biologics

Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first event counter counts the occurrences of a type of event within the processor and outputs a signal to activate a second event counter in response to reaching a first predefined count. The second event counter counts the occurrences of the type of event within the processor and causes an interrupt of the processor in response to reaching a second predefined count.

Causing an interrupt based on event count

A method comprises filtering branch trap events at a branch event filter, monitoring a branch event filter to capture indirect branch trap events that cause a control flow trap exception, receiving the indirect branch trap events at a handler and the handler processing the indirect branch trap events.

Execution profiling mechanism

In accordance with embodiments disclosed herein, there is provided systems and methods for using thresholds to gate timing packet generation in a tracing system (TS). For example, the method may include generating and outputting a trace data (TD) packet into a packet log. The method also includes generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.

Using thresholds to gate timing packet generation in a tracing system

A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.

Real time instruction trace processors, methods, and systems

A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device. The processing device further includes at least one register communicably coupled to the LBR counter, the at least one register to provide an LBR structure comprising a plurality of LBR entries. An LBR entry of the plurality of LBR entries includes an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter in response to creation of the LBR entry.

Elapsed cycle timer in last branch records

Growing community of inventors

Atlit, Israel

Ofer Levy