Intel Corporation

Ofer J Nathan

Nadav Shulman

Varghese George

Sanjeev S Jahagirdar

Jose P Allarey

Oren Lamdan

Tomer Ziv

Eliezer Weissmann

Alon Naveh

Tsvika Kurts

Krishnakanth Venkata Sistla

Alexander Gendler

Michael Mishaeli

Su Wei Lim

Ofer Levy

Daniel J Ragland

Tal Kuzi

Ernest Knoll

Esfir Natanzon

Itai Feit

Ariel Szapiro

Ariel Gur

Ariel Sabba

Siang Lin Tan

Shani Rehana

Ming Chew Lee

Ori Levy

John M Zavertnik

An apparatus is provided which comprises: an input/output (I/O) port; an adaptor; a physical layer to interface between the I/O port and the adaptor; a first controller associated with a first type of communication; and a second controller associated with a second type of communication, wherein the adaptor is to selectively couple the I/O port, via the physical layer, to one of the first controller or the second controller, based at least in part on a type of device coupled to the I/O port.

Integrated universal serial bus (USB) type-C switching

A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.

Method and apparatus for automatic adaptive voltage control

Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

Changing the clock frequency of a computing device

In an embodiment, a processor includes a master counter to store a time stamp count for the processor, and multiple cores each including a core counter to store core time stamp counts. The processor also includes synchronization logic to, in response to a de-synchronization event in a core: obtain a value of the master counter; initiate a first core counter using the value of the master counter, where the first core counter is included in the first core; compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and in response to a determination that the synchronization digit does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal. Other embodiments are described and claimed.

Synchronization of domain counters

The present invention may provide a system with a fixed clock to provide a fixed clock signal, and a variable clock to provide a variable clock signal. The system may also include a chipset with a chipset time stamp counter (TSC) based on the fixed clock signal. A processor may include a fast counter that may be based on the variable clock signal and generate a fast count value. A slow counter may download a time stamp value based on the chipset TSC at wakeup. The slow counter may be based on the fixed clock signal and may generate a slow count value. A central TSC may combine the fast count and slow count value to generate a central TSC value.

Time keeping in unknown and unstable clock architecture

A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.

Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates

With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.

Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor

A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations () the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and () the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.

Method, apparatus, and system for optimizing frequency and performance in a multi-die microprocessor

An integral breakpoint detector. The integral breakpoint detector may be included in a processor, a chipset, or another bus agent. One embodiment is an apparatus such as an integrated circuit that includes a bus interface to communicate with a bus and an integrated breakpoint detector. The bus interface may include a bus tracker which communicates with the integrated breakpoint detector. The integrated breakpoint detector is to provide a first indication responsive to an occurrence of a predetermined relationship between a programmable value and a condition related to the bus.

Integrated breakpoint detector and associated multi-level breakpoint techniques

Growing community of inventors

Kiryat Tivon, Israel

Ofer J Nathan