Mellanox Technologies, Ltd.

Ofer Hayut

Noam Bloch

Michael Kagan

Ariel Shachar

Liran Liss

Ariel Shahar

Shlomo Raikin

Richard Leigh Graham

Liron Mula

Gil Bloch

Yaron Haviv

Hillel Chapman

Adi Menachem

Shahaf Shuler

Yossef Itigin

Gilad Shainer

Ran Avraham Koren

Omer Sella

Nir Getter

Elad Persiko

A method for data communication includes submitting from a host processor to a network interface controller (NIC) during a first time period first work items instructing the NIC to transmit over a network packets containing respective data. The first work items include pointer-based work items, which contain a pointer to the respective data in a memory of the host processor, and inline work items, which contain the respective data. The performance of the NIC is measured in transmitting the packets during the first time period. During a second time period, subsequent to the first time period, the host processor submits second work items to the NIC while deciding automatically, under control of software running on the host processor and based on the measured performance during the first time period, how many of the second work items are to be pointer-based and how many are to be inline work items.

Automated control of descriptor type for packet transmission

A Network Interface Controller (NIC) includes a network interface, a peer interface and steering logic. The network interface is configured to receive incoming packets from a communication network. The peer interface is configured to communicate with a peer NIC not via the communication network. The steering logic is configured to classify the packets received over the network interface into first incoming packets that are destined to a local Central Processing Unit (CPU) served by the NIC, and second incoming packets that are destined to a remote CPU served by the peer NIC, to forward the first incoming packets to the local CPU, and to forward the second incoming packets to the peer NIC over the peer interface not via the communication network.

Efficient management of network traffic in a multi-CPU server

A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more work requests that are derived from an operation to be executed by the node. The NI maintains a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the work requests via the host interface, and to execute the work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

Network operation offloading for collective operations

A method for communication includes posting, by a software process, a set of buffers in a memory of a host processor and creating in the memory a list of labels associated respectively with the buffers. The software process pushes a first part of the list to a network interface controller (NIC), while retaining a second part of the list in the memory under control of the software process. Upon receiving a message containing a label, sent over a network, the NIC compares the label to the labels in the first part of the list and, upon finding a match to the label, writes data conveyed by the message to a buffer in the memory. Upon a failure to find the match in the first part of the list, the NIC passes the message from the NIC to the software process for handling using the second part of the list.

Hybrid tag matching

A method for network access of remote memory directly from a local instruction stream using conventional loads and stores. In cases where network IO access (a network phase) cannot overlap a compute phase, a direct network access from the instruction stream greatly decreases latency in CPU processing. The network is treated as yet another memory that can be directly read from, or written to, by the CPU. Network access can be done directly from the instruction stream using regular loads and stores. Example scenarios where synchronous network access can be beneficial are SHMEM (symmetric hierarchical memory access) usages (where the program directly reads/writes remote memory), and scenarios where part of system memory (for example DDR) can reside over a network and made accessible by demand to different CPUs.

Direct IO access from a CPU's instruction stream

A network interface includes a host interface for communicating with a node, and circuitry which is configured to communicate with one or more other nodes over a communication network so as to carry out, jointly with one or more other nodes, a redundant storage operation that includes a redundancy calculation, including performing the redundancy calculation on behalf of the node.

Offloading node CPU in distributed redundant storage systems

A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to write completion reports to the system memory, including first completion reports of a first data size and second completion reports of a second data size, which is smaller than the first data size.

Reducing size of completion notifications

A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to generate completion reports and to write a plurality of the completion reports to the system memory via the bus together in a single bus transaction.

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Kvutzat Yavne, Israel

Ofer Hayut