Marvell Israel (misl) Ltd.

Ofer Benjamin

Eldad Bar-Lev

Yosef Solt

Eli Kurin

Igal Sade

Asaf Idan

Nasim Nasser

A method includes receiving a group of logic signals to be sampled at a common sampling timing. Individual time delays, which individually align each of the logic signals to the common sampling timing, are selected for the respective logic signals in the group. Each of the logic signals is delayed by the respective selected individual time delay, and the entire group of the delayed logic signals is sampled at the common sampling timing.

Optimal sampling of data-bus signals using configurable individual time delays

A testing method includes measuring an electrical parameter of a device under test (DUT) and a corresponding temperature of the DUT one or more times, determining coefficients in a pre-constructed model based on a plurality of measured values of the electrical parameter and corresponding measured temperatures to characterize a relationship of the electrical parameter to the temperature, and determining a quality of the DUT based on the model and a limit value of the electrical parameter at a specified temperature. The model is pre-constructed to characterize the relationship of the electrical parameter to the temperature with the coefficients that are DUT-dependent variables.

Method and apparatus for testing IC

Some of the embodiments of the present disclosure provide a method including: communicating, by a first pin of an integrated circuit, with a device over a communication link, wherein the first pin is associated with a first impedance; selecting a plurality of impedance values for the first impedance; for ones of the plurality of impedance values, (i) transmitting a corresponding digital signal from the first pin over the communication link and (ii) generating a corresponding signal eye opening for the corresponding digital signal, such that a plurality of signal eye openings corresponding to a plurality of digitals signals for the corresponding plurality of impedance values are generated; comparing the plurality of signal eye openings; selecting a first impedance value of the plurality of impedance values; and transmitting signals over the communication link, with the first impedance being tuned to the first impedance value.

Impedance and duty cycle calibration in a driver circuit and a receiver circuit

Some of the embodiments of the present disclosure provide an integrated circuit communicating with a device over a multi-pin parallel bus, the integrated circuit comprising: at least a first pin and a second pin to communicate with the device over the multi-pin parallel bus; and an impedance tuning module disposed in the integrated circuit and configured to tune an impedance value of a first impedance associated the first pin separately from tuning an impedance value of a second impedance associated with the second pin.

Impedance calibration in a driver circuit and a receiver circuit

Aspects of the disclosure provide a method for testing. The method includes determining an electrical characteristic of an integrated circuit (IC), subjecting the IC to a stress test, characterizing the electrical characteristic of the IC subsequently to subjecting the IC to the stress test, and determining a quality attribute of the IC based on a comparison of the respective electrical characteristics of the IC before and after subjecting the IC to the stress test.

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Haifa, Israel

Ofer Benjamin