Qimonda Ag

Infineon Technologies Ag

Odo Wunnicke

Peter Moll

Till Schloesser

Johannes Heitmann

Rolf Weis

Peter Baars

Stefan Tegen

Stephan Kudelka

Ulrike Gruening-von Schwerin

Klaus Muemmler

Stefan Jakschik

Peter Lahnor

Kristin Schupke

Florian Schnabel

Andreas Orth

Wolfgang Henke

Wolfgang Mueller

A method for forming an integrated circuit having openings in a mold layer and for producing capacitors is disclosed. In one embodiment, nanotubes or nanowires are grown vertically on a horizontal substrate surface. The nanotubes or nanowires serve as a template for forming openings in a mold layer. The substrate is covered with a mold material after the formation of the nanowires or nanotubes. One embodiment provides mold layers having openings with a much higher aspect ratio.

Methods for forming an integrated circuit, including openings in a mold layer from nanowires or nanotubes

A method of forming an integrated circuit having a capacitor is disclosed. In one embodiment, the method includes forming a capacitor element with a first electrode, a dielectric layer and a second electrode. The capacitor element is formed using a support layer.

Method of producing an integrated circuit having a capacitor with a supporting layer

A structure and method of forming a capacitor is described. In one embodiment, the capacitor includes a cylindrical first electrode having an inner portion bounded by a bottom surface and an inner sidewall surface, the first electrode further having an outer sidewall, the first electrode being formed from a conductive material. An insulating fill material is disposed within the inner portion of the first electrode. A capacitor dielectric is disposed adjacent at least a portion of the outer sidewall of the first electrode. A second electrode is disposed adjacent the outer sidewall of the first electrode and separated therefrom by the capacitor dielectric. The second electrode is not formed within the inner portion of the first electrode.

Semiconductor component with MIM capacitor

A method for forming a capacitor structure, according to which the following consecutive steps are executed: providing a substrate having on its surface contact pads and a dielectric mold provided with at least one trench leaving exposed the contact pads; forming a first conductive layer on side walls of the trench in a top region of the trench the conductive layer being without contact to the contact pads; depositing a first dielectric layer; depositing a second conductive layer on the contact pad and on the side walls of the trench; depositing a second dielectric layer; depositing a third conductive layer; and forming a vertical plug interconnecting the first conductive layer and the third conductive layer.

Method for forming a capacitor structure

A method for manufacturing a capacitor electrode structure, according to which the following steps are executed: A substrate is provided, which comprises contact pads arranged in lines and rows on a surface of the substrate. The lines are non-parallel to the rows. A first mold is applied on the substrate. At least one first trench is formed into the first mold above the contact pads. The first trench spans over at least two contact pads arranged in one row. A first dielectric layer is applied on side walls of the at least one first trench for forming first supporting walls. A second mold is applied on the substrate. At least one second trench is formed into the second mold above the contact pads. The second trench spans over at least two contact pads arranged in one line. A second dielectric layer is applied on side walls of the at least one second trench for forming second supporting walls. And a conductive layer is applied on the first and second supporting walls for forming a first electrode of the capacitor structure.

Method for manufacturing a capacitor electrode structure

A capacitor for a dynamic semiconductor memory cell, a memory and method of making a memory is disclosed. In one embodiment, a storage electrode of the capacitor has a pad-shaped lower section and a cup-shaped upper section, which is placed on top of the lower section. A lower section of a backside electrode encloses the pad-shaped section of the storage electrode. An upper section of the backside electrode is enclosed by the cup-shaped upper section of the storage electrode. A first capacitor dielectric separates the lower sections of the backside and the storage electrodes. A second capacitor dielectric separates the upper sections of the backside and the storage electrodes. The electrode area of the capacitor is enlarged while the requirements for the deposition of the capacitor dielectric are relaxed. Aspect ratios for deposition and etching processes are reduced.

Storage capacitor for semiconductor memory cells and method of manufacturing a storage capacitor

A method produces stacked capacitors for dynamic memory cells, in which a number of trenches () are formed in the masking layer (), each trench () being arranged above a respective contact plug () and extending from the top () of the masking layer () to the contact plugs (). A conductive layer () covers the side walls () of the trenches () and the contact plugs () in order to form a first electrode () of a stacked capacitor (). In an upper region (), which is remote from the contact stack (), the conductive layer () is replaced by an insulating layer, so that it is not possible for a short circuit to arise in the event of any adhesion between adjacent electrodes.

Growing community of inventors

Dresden, Germany

Odo Wunnicke