Intel Corporation

Oded Oliron Liron

Uri Frank

Marina Sharkansky

Solomon B Trainin

Zeev Sperber

Mohammad A Abdallah

Ittai Anati

Jorge Myszne

Ronen Levi

Nadav Szanto

Netanel Nati Bar-David

Michael Shusterman

Rom Leor

Levi Ronen

Shimon Lavi

A wireless communication device including one or more processors configured to determine a device state; determine a data rate of a signal; determine a latency tolerance value based on the data rate and the device state; and generate a message comprising the latency tolerance value. The wireless communication device may further be configured to determined if the latency tolerance value is a duration associated with a device reception or transmission.

Methods and devices for adaptive rate based latency tolerance reporting

Techniques are provided for managing the forwarding of a data stream to respective cores of a multi-core system, in which the incoming data stream is processed in a hardware machine prior to forwarding the data stream to respective cores. The techniques may include the hardware machine executing an algorithm to identify frames in the data stream having a fake hole therein, generating metadata, and attaching the metadata to any frame in which a fake hole is identified. The metadata may instruct a core that receives the respective frame in which a fake hole has been identified to ignore the fake hole in that respective frame. Also in the algorithm, the hardware machine identifies frames in which a real hole exists and maintains a database log of the real holes and the respective cores among the multiple cores that receive the data stream with the real holes therein, together with a notification to the respective core.

Managing a data stream in a multicore system

A transmit and receive machine (TRM) is part of a medium access controller (MAC), in support of the 802.11 wireless standard. The TRM is a control machine that changes the MAC within which it resides from a purely software-based MAC into a software and hardware management system. Timing-critical tasks that were once performed by the embedded processor of the MAC are performed by the TRM. This change enables the MAC to operate at a high speed while the TRM maintains high accuracy of transmit and receive timing operations.

Transmit and receive transition accelerator

A method and system including transmitting data in an architectural format between execution units in a multi-type instruction set architecture and converting data received in the architectural format to an internal format and data output in the internal format to the architectural format based on an operation code and a data type of a microinstruction.

System and method of converting data formats and communicating between execution units

Embodiments of the present invention provide a method, apparatus and system of radar detection. The method, according to some demonstrative embodiments of the invention, may include comparing an energy level of signals received over a wireless communication channel to a threshold; during operation of a processor, if the energy level is above the threshold, determining independently of the processor one or more time values related to said signals; and if the energy level decreases to or below the threshold, interrupting the operation of the processor to determine, based on the time values, one or more parameters of a detection time period during which the energy level was above the threshold. Other embodiments are described and claimed.

System, method and device of radar detection

A method and apparatus for an apparatus and method for reduction of power consumption in OS that use flat segmentation memory model are described. In one embodiment, the method includes monitoring a segment register to detect a segment register update operation. Once the segment register update operation is detected, a code/data segment contained within the segment register is identified as one of a segmented code/data segment and a flat code/data segment. Once detected, the segment register is updated according to whether the segment is flat or segmented. Accordingly, when a segment register read is performed, one or more updated bits within the segment register are used to identify the code/data read from the segment register as either flat or segmented.

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Ha, Israel

Oded Oliron Liron