Motorola Corporation

Marvell Asia Pte., Ltd.

Ikanos Communications, Inc.

Oded Norman

Eitan E Rosen

Yoram Salant

Moshe Refaeli

Paul McAlinden

Boaz Perlman

Vladimir Koifman

John J Vaglica

Jean Khawand

Natan Baron

Arvind S Arora

Zvika Rozenshein

Boris Zabarski

Thomas Edward Oberhauser

Elchanan Rushinek

Gilad Hazan

Eliezer Zand

Noam Benayahu

David Sitbon

Eyal Salomon

A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.

Method and apparatus for controlling clock cycle time

The present invention provides techniques for efficiently determining a minimum or maximum of a plurality of values and the index of the minimum using registers of a processor. The present invention also provides for various processor instructions for determining the minimum/maximum and index of two or more values. The present invention finds particular benefit in implementing heaps and in systems utilizing Weighted Fair Queuing (WFQ).

Minimum processor instruction for implementing weighted fair queuing and other priority queuing

A data processing system has a pipelined architecture and looping capability that allows a sequence of instruction execution sets to be repeated N times. The data processing system has an internal memory module data arithmetic logic units, and a program sequencer for fetching instruction fetch sets, dispatching instructions out of a instruction execution set to the data arithmetic logic units, and controlling the execution of nested loops. The instruction execution set is a subset of the instruction fetch set. The instruction execution set that initiates the conditional jump operation has a prefix instruction for initiating the conditional jump operation.

Data processing system and method for implementing zero overhead loops using a first or second prefix instruction for initiating conditional jump operations

A radio ( ) with a burst event execution and time synchronization apparatus ( ) executes instructions during and after performing time synchronization between a mobile unit and a base station. Both base station ( ) and mobile radio ( ) have internal timer units ( ). Mobile radio ( ) timing unit ( ) is reset during synchronization between the mobile radio ( ) and the base station ( ). The control unit ( ) writes instructions I(i) including their execution times T(i) to a memory bank ( ) within the mobile radio ( ). Execution logic ( ) within mobile radio ( ) executes instruction operands O(i) when execution time T(i) is equal or smaller then a timing count signal received from the timer unit ( ). When a time synchronization reset causes the radio ( ) time count to jump past queued instructions they can be executed immediately in a burst or delayed until the next communication frame.

Radio with burst event execution apparatus and method therefore

A mobile radio ( ) with a synchronization apparatus ( ) executes a method ( ) for time synchronizing the radio ( ) and a base station ( ). Base station ( ) and radio ( ) have internal timers ( ). A control unit ( ) in the radio ( ) receives a signal ( ) from the base station ( ) and determines the difference F between timers ( ) in the base ( ) and mobile ( ). The control unit ( ) writes instructions I(i) and their execution times T(i) to a memory ( ) within the radio ( ). One of these instructions I(N) reloads the radio timing counter ( ) with a corrected value C&equals;f(F,B) at a predetermined time T(N)&equals;B which avoids conflicts with other operations of the radio ( ).

Radio with synchronization apparatus and method therefore

A radio (,) executes a method (,) for entering and exiting a halt status. Radio (,) has a control unit (,) and an internal timing unit (,). The timing unit (,) has execution logic (,), a status register (,) a counter (,) and a clock source (,). The control unit (,) writes instructions I(i) and their execution times T(i) to a memory (,) within the execution logic (,). One of these instructions is a 'SWITCH CLOCK' instruction causing the timing unit (,) to switch between clock signals. One of the instructions is 'HALT COUNTER' causing the radio (,) to enter a halt state. The radio (,) can be synchronized to the end of a first communication frame received by it after exiting a halt state.

Radio with halting apparatus and method

A communications system includes multiple processors (14, 16) and a protocol timer (18). The protocol timer (18) controls the timing of events in the communications system and operates autonomously after it is loaded with initial instructions by one of the multiple processors (14, 16). The protocol timer (18) utilizes a frame event table (50) and a macro event table (46, 48) to trigger events and to generate interrupts of the multiple processors (14, 16). By allowing the protocol timer (18) to operate autonomously, the processors (14, 16) are relieved of timing control, and can be powered down when not in use, thus reducing power consumption of the communications system. Also, by using the protocol timer (18) to control the timing of events, software related errors and interrupt latencies are reduced.

Data processing system having a protocol timer for autonomously

A rate multiplier for rate multiplying a pulse train comprising: an accumulator, a multiplexer for selecting one of a first and a second number of different signs to feed to the accumulator, and a pulse train gate for providing or blocking the pulse train, wherein the multiplexer and the pulse train gate are controlled by the MSB output signal of the accumulator.

Binary rate multiplier

To execute a three-dimensional DMA transfer, a transfer counter register (76), which is partitioned into three sections, is loaded with initial counter values. Each section of the counter register (76) is independently controlled by a counter (72, 73, 74). Data is transferred from consecutive generated addresses for a first predetermined number of times as determined by the value in the first section of the counter register (76). An offset value is then added to a last generated address. The process is repeated for a second predetermined number of times. Then another offset value is added to the generated address. This entire process is repeated for a given number of times as determined by the third section of the register (76). The initial counter values are reloaded into counter register (76) from a backup register (77), insuring that a DMA controller (80) is ready if a new transfer request requires the same counter values as the previous transfer.

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Pardesia, Israel

Oded Norman