Intel Corporation

Mellanox Technologies, Ltd.

Oded Lempel

Lihu Rappoport

Robert Valentine

Chen Koren

Ron Gabor

Roman Surgutchik

Franck Sala

Lior Libis

Ittai Anati

Ido Ouziel

Ilhyun Kim

Gregory Pribush

Guy Peled

Mohan J Kumar

Gad Shlomo Sheaffer

Mark B Rosenbluth

Ronny Ronen

Ilan Pardo

Idan Burstein

Michael Mishaeli

Ganapati Srinivasa

Tsvika Kurts

Theodros Yigzaw

Jose Andy Vargas

Julius Yuli Mandelblat

Zeev Offen

Larisa Novakovsky

Michael A Julier

Hisham Shafi

Geeyarpuram N Santhanakrishnan

Nicolas I Kacevas

Thomas M Johnson

Rui Xu

Nicolas Kacevas

Haim Lustig

Eran Altshuler

Tsofia Eshel

Gad S Shaeffer

In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.

Payload cache

An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.

Apparatus and method for implement a multi-level memory hierarchy

Methods and apparatus for inclusion of TLB (translation look-aside buffer) in processor micro-op caches are disclosed. Some embodiments for inclusion of TLB entries have micro-op cache inclusion fields, which are set responsive to accessing the TLB entry. Inclusion logic may the flush the micro-op cache or portions of the micro-op cache and clear corresponding inclusion fields responsive to a replacement or invalidation of a TLB entry whenever its associated inclusion field had been set. Front-end processor state may also be cleared and instructions refetched when replacement resulted from a TLB miss.

Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor

Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.

Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor

Embodiments of the present invention relate to detecting and clearing a soft error in a cache.

System and method for soft error handling

A system and method of early branch prediction in a processor to evaluate, typically before a full branch prediction is made, ways in a branch target buffer to determine if any of said ways corresponds to a valid unconditional branch, and upon such determination, to generate a signal to prevent a read of a next sequential chunk.

Preventing a read of a next sequential chunk in branch prediction of a subject chunk

Embodiments of the present invention relate to displaying images from memory. A plurality of pixel attributes are retrieved from memory in a single memory transaction. At least one attribute corresponds to one scan line of a display and another attribute corresponds to another scan line of the display. A portion of one scan line using the corresponding pixel attribute is displayed. The pixel attributes corresponding to another scan line is stored in a buffer.

Display of images from tiled memory

A processor includes a host interface unit capable of generating at least one branch trace message (BTM), the host interface unit is coupled to a memory so as to store the at least one BTM in the memory and the processor is embodied on an integrated circuit (IC).

Method and apparatus for branch trace message scheme

A system and method for predicting a branch target for a current instruction in a microprocessor, the system comprising a cache storing indirect branch instructions and a path register. The path register is updated on certain branches by an XOR operation on the path register and the branch instruction, followed by the addition of one or more bits to the register. The cache is indexed by performing an operation on a portion of the current instruction address and the path register; the entry returned, if any, may be used to predict the target of the current instruction.

Method and system for branch target prediction using path information

A method and apparatus for preventing over-prefetching from a buffer receives an address of a last data set item in a data buffer, and reads data from the data buffer into a read streamer buffer starting at a data buffer start address until the address of said last item.

Managing prefetching from a data buffer

A method and apparatus for fast unsigned integral division, utilized in compositing images, sounds or other data, is provided. Compositing utilizes a division step. The divisor is the value of two to the Nth power minus one. The division comprises the steps of making a copy of the first number, thus producing a third number. The first number is shifted to the right by N. The third number is biased, and is then added to the first number. The resultant number is shifted right by N. This process results in a division by 2.sup.N -1, with short latency instructions, instead of the long latency instructions usually used for division operations.

Method and apparatus for fast unsigned integral division

An apparatus includes a data array, control logic, an entry candidate table, and a future target table. The control logic is coupled to the data array and adapted to store at least one trace segment of instructions into the data array. The entry candidate table is coupled to the control logic and is adapted to store offset information related to the position of a selected instruction within the trace segment. The future target table is coupled to the control logic and adapted to store a potential entry point into the trace segment. A method for caching instructions includes storing a first plurality of instructions in a first trace segment. A control flow instruction is identified from the first plurality of instructions and the outcome of the control flow instruction is predicted. The control flow instruction has a predicted taken target address and a predicted not-taken target address corresponding to the outcome predicted. The predicted not-taken target address is stored.

Method and apparatus for identifying potential entry points into trace

An apparatus includes a data array and control logic. The control logic is coupled to the data array and adapted to store at least one trace segment of instructions into the data array. The control logic allows the instructions of the trace segment to be sequentially retrieved beginning with a selected instruction. The selected instruction is offset from the first instruction of the trace segment. A method for caching instructions includes storing a first plurality of instructions in a first trace segment. A selected instruction of the first plurality of instructions is identified within the first trace segment. The selected instruction is offset from the first instruction of the first trace segment. The offset information related to the position of the selected instruction within the first trace segment is stored. A method for retrieving cached instructions, wherein the cached instructions are stored in a trace segment and the trace segment has a head instruction, includes determining a linear address related to a selected instruction to be retrieved. An entry point into the trace segment corresponding to the linear address is identified. The entry point is offset from the head instruction. The selected instruction is retrieved from the entry point within the identified trace segment.

Method and apparatus for caching trace segments with multiple entry

A branch prediction unit includes a first branch target buffer, a second branch target buffer, and a static predictor. The first branch target buffer is adapted for storing a first plurality of branch history entries. The second branch target buffer is adapted for storing a second plurality of branch history entries. The static predictor is adapted for determining a static branch prediction for an encountered branch instruction. The second branch target buffer is further adapted to allocate a branch history entry based on the static prediction. A method for predicting program branches in a microprocessor includes fetching a program instruction to be executed by the microprocessor. It is determined if an entry corresponding to the program instruction is stored in a first branch target buffer, and if an entry corresponding to the program instruction is stored in a second branch target buffer. It is determined if the program instruction is a branch instruction. A static prediction is determined for the branch instruction. A branch history entry is allocated in the second branch target buffer based on the static prediction if the first and second branch target buffers do not contain entries corresponding to the program instruction.

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Amikam, Israel

Oded Lempel