International Business Machines Corporation

Ay Dee Kay LLC

Semiconductor Components Industries, LLC

Oded Katz

Tom Heller

Danny Elad

Israel A Wagner

Benny Sheinman

Run Levinger

Roee Ben-Yishay

Dan Ramon

Michael Grubman

Yanir Schwartz

Dan Corcos

Christopher B Reynolds

Elazar Kachir

Moshe Leibowitz

Joseph H Underwood

Nadav Mazor

Roi Carmon

Lansing D Pickup

Rina Kipnis

William R Andersen

Elad Danny

Assaf Barak

Eli Bloch

Anastasia Ester Kapchits

Yaniv Maroz

An improved circuit configuration is disclosed for calibrating and/or verifying the operation of phase shifters in a phased array radar system. In one illustrative embodiment, a method includes: (i) programming a set of phase shifters to convert a radio frequency signal into a set of channel signals; (ii) splitting off a monitor signal from each channel signal while coupling the set of channel signals to a set of antenna feeds; and (iii) while taking the monitor signals in pairs associated with adjacent channels, measuring a relative phase between each pair of monitor signals.

Radar array phase shifter verification

A split-steer amplifier with an invertible phase output, includes a first transistor having its base coupled to a positive node of an input port, its emitter coupled to ground, and collector connected to a positive intermediate node; a second transistor having its base coupled to a negative node of the input port, its emitter coupled to ground, and collector connected to a negative intermediate node; and multiple output ports each having a transistor arrangement operable to couple a positive node of that output port to the positive intermediate node and a negative node of that output port to the negative intermediate node, operable to couple the positive node of that output port to the negative intermediate node and the negative node of that output port to the positive intermediate node, and operable to decouple the positive node and the negative node of that output port from the intermediate nodes.

Split-steer amplifier with invertible output

Illustrative methods and circuits to verify operation of phase shifters. One illustrative method includes: obtaining a first set of in-phase and quadrature components (I,Q) of a phase shifter output signal with a first setting; measuring a second set of components (I,Q) with a second setting, the second setting being offset from the first by a predetermined phase difference; and combining the first and second sets to determine whether their relationship corresponds to the predetermined phase difference. An illustrative transmitter includes: a phase shifter, an I/Q mixer, and a processing circuit. The phase shifter converts a transmit signal into an output signal having a programmable phase shift. The I/Q mixer mixes the output signal with a reference signal to obtain in-phase and quadrature components of the output signal. The processing circuit is coupled to the I/Q mixer implement the disclosed method.

Phase shifter self-test

An array of one or more integrated circuits includes at least one local input port to receive a chirp signal from a local generator; one or more primary input ports to each receive a respective chirp signal from a remote source; a primary switch arrangement operable to switch between the chirp signals from the at least one local input port and the one or more primary input ports to produce a composite signal having a chirp sequence with at least one chirp that begins during a settling period of a previous chirp; and one or more primary output ports to supply a local oscillator signal to a transmitter and a receiver based on the composite signal. The roles of master circuit and follower circuit can change during operation of the array.

Chirp sequence synthesis in a dynamic distribution network

A multi-antenna signal encoding method comprises receiving an antenna signal and a reference signal a first mixer; producing, using the first mixer, a down-converted signal based on the antenna signal and the reference signal; receiving, at one or more second mixers, second antenna signals and second reference signals orthogonal to the first reference signal; producing one or more second down-converted signals based on the one or more second antenna signals and the one or more second reference signals; converting, using an analog-to-digital converter, a summation signal corresponding to a sum of the first down-converted signal and the one or more second down-converted signals, into a digital receive-signal; and extracting, at a processor, a plurality of digital signals from the digital receive-signal, wherein each of the plurality of digital signals corresponds to one of the first antenna signal and the one or more second antenna signals.

MIMO radar with receive antenna multiplexing

This invention relates to assemblies and processes for increasing the bandwidth of differential passive elements. The use of a floating plane in differential transmission lines is disclosed. One such assembly is a broadband balun having high even mode effective impedance, thus degrading the even-mode propagation or matching, and maintaining the desired odd mode effective impedance. Other assemblies can include line couplers, hybrid couplers, RF chokes with back-to-back baluns, and other elements, such as balanced filters.

Bandwidth increase method for differential passive elements

A system comprises a differential phase shifter based on a differential coupled line coupler that can include a ground metal layer, a bottom metal layer and a top metal layer. The differential line coupler can include differential input lines comprising two metal stack layers (top and bottom), which are arranged diagonally, and the differential output lines are arranged in a complementary diagonal configuration. This layout configuration overcomes the asymmetry caused by the difference in metal layer thickness and width difference, as well as a periphery effect such as the distance to a ground plane or substrate. The proposed diagonal layout configuration balances the characteristic impedance and phase accumulation on each coupled wire of the differential coupled line coupler, which improves the performance of the phase shifter, e.g. lower insertion loss and wider phase tuning range.

Integrated differential phase shifter based on coupled wire coupler using a diagonal configuration

Aspects of the present invention include a circuit that includes an input balun circuit responsive to an input signal, the input balun circuit being configured to provide two output signals that are out of phase with each other. The circuit further includes an actual switched amplification stage configured to direct one of the balun output signals to a phase inverter output, and a replica switched amplification stage connected in parallel with the actual switched amplification stage, wherein the actual switched amplification stage and the replica switched amplification stage are responsive to the two output signals from the input balun circuit to direct one of the balun output signals to the phase inverter output, and wherein the actual switched amplification stage and the replica switched amplification stage are configured to have a constant load impedance for both switch states that matches an impedance of the input balun circuit.

Balun based phase inverter using replica load

An electronic sub-integer frequency divider circuit, including: a phase rotator circuit, a clock circuitry, a pulse generator which is configured to: (a) receive a plurality of signals having a period TP and of different phases; (b) based on a control command, to process a second clock signal and one or more of the plurality of signals, to produce a second signal which includes S pulses in each period TP; and (c) process the second signal and a first clock signal to produce a regulating signal by which the phase rotator circuit is controlled; and an output interface configured to provide a sub-integer output signal whose frequency is responsive to the regulating signal.

System, a method and a computer program product for electronic sub-integer frequency division

A frequency quadrupler comprises a balanced topology which increases broadband odd harmonic suppression. The frequency quadrupler is constructed in a cascode configuration which is a two-stage amplifier composed of a transconductance amplifier followed by a current buffer. The cascode is constructed with common emitter (CE) and common base (CB) stages which further improves the multiplier frequency response. The cascode configuration enables a notch filter to be placed between the common emitter and common base stages to reduce 2harmonic generation and thereby increase 4harmonic output power, generation efficiency and conversion gain. To cancel 4harmonic components at the input that may destructively interfere with the output signal, capacitors are placed at the input of the common emitter stage, which in conjunction with the parasitic base wire inductance, form a notch filter to short the 4harmonic.

High conversion gain high suppression balanced cascode frequency quadrupler

A computer-implemented method identifies at least one proprietary geometric figure from a plurality of geometric figures within a design data layout format file. The proprietary geometric figure in the design data layout format file may be replaced with a placeholder geometric figure. Cell names and connection names associated with the proprietary geometric figure are renamed from a netlist file that defines electrical connections between the geometric figures with obfuscating names. A modified design data layout format file may be generated that includes the placeholder geometric figure and a modified netlist file including the obfuscating names. The modified file enables IC designers to complete their design and checking activities, but inhibits reverse-engineering of the proprietary geometric & netlist data.

Method for providing a secure 'gray box' view proprietary IP

A feedback mechanism to reduce current variation observed in a current reference branch circuit by using body voltage control to compensate process, temperature and supply voltage variations. The current reference output voltage, which is proportional to the reference current, is sampled into a feedback loop, which controls the field effect transistor body voltage. The method and mechanism uses Corner Robust Current Reference in order to keep the design simple and diminish variation between Process Voltage Temperature (PVT) corners. This method exhibits small variation in the reference current magnitude.

Method and mechanism to reduce current variation in a current reference branch circuit

Some demonstrative embodiments of the invention include a method, apparatus and system of generating a random number. A random number generator may include, for example, a plurality of different random-number-generation modules adapted to generate random bits at a plurality of bit paths; and a combiner adapted to combine the bits of the plurality of paths. Other embodiments are described and claimed.

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Ganei-Tikva, Israel

Oded Katz