Lucent Technologies Inc.

Agere Systems Inc.

Obed Duardo

Yi-Jen Chiu

Rajesh Hingorani

Paul Albin Wilford

James A Dahlberg

Xianguo Cao

Bo Ye

A method is disclosed for decoding multiple-coded symbols from a coded input symbol stream in a single clock cycle. The method constructs an original Huffman look-up table by extending the associated Huffman tree to decode multiple symbols in one clock cycle in a first embodiment and decodes multiple DCT coefficient symbols in an alternate embodiment. An advantage of the method is that the depth of the new Huffman tree is adjustable thereby making the method easily adaptable to various hardware architectures. A further advantage of the present invention is that the decoding process speed is significantly increased while the size of the lookup table is nominally increased.

Adaptive variable length decoding method

A double data rate (DDR) synchronous dynamic RAM (SDRAM), or DDR-SDRAM, memory controller employing a delay locked loop (DLL) circuit to delay an SDRAM data strobe (DQS) signal to the center, or 'eye' of the read data window. However, in distinction from conventional techniques, the initial delay determined by the DLL is fine tuned with an offset determined by a memory test. Moreover, in an additional embodiment, the delay may be further adjusted during operation to compensate for environmental conditions by a PVT (process, value, temperature) circuit.

Programmable data strobe offset with DLL for double data rate (DDR) RAM memory

A delay compensation circuit that determines the effects of process, voltage, and temperature (PVT) conditions of a chip by measuring the effective delay time of delay components inside the chip. The delay compensation circuit includes a plurality of sampler modules, each of which receives a delayed clock signal from one of a series of delay cells within a tapped delay circuit. The delay compensation circuit generates an output value based on the total number of sampling modules that lock into a fixed input signal using the delayed clock signals. Since the delay time of each delay cell changes based on variations of PVT conditions, the output values generated by the delay compensation circuit are determinate of PVT conditions in the chip. These output values can be used to design components to compensate for variances in PVT conditions or to control a variable delay component based on detected PVT conditions.

Delay compensation circuit

A method is disclosed for decoding multiple-coded symbols from a coded input symbol stream in a single clock cycle. The method constructs an original Huffman look-up table by extending the associated Huffman tree to decode multiple symbols in one clock cycle in a first embodiment and decodes multiple DCT coefficient symbols in an alternate embodiment. An advantage of the method is that the depth of the new Huffman tree is adjustable thereby making the method easily adaptable to various hardware architectures. A further advantage of the present invention is that the decoding process speed is significantly increased while the size of the look-up table is nominally increased.

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Coral Springs, FL, United States of America

Obed Duardo