Infineon Technologies Ag

International Business Machines Corporation

O Seo Park

Sun-Oo Kim

Wai-Kin Li

Klaus Herold

Todd Christopher Bailey

Sajan Marokkey

Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.

Methods of manufacturing semiconductor devices and optical proximity correction

Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features.

Semiconductor devices and methods of manufacturing thereof

A design for a crack stop and moisture barrier for a semiconductor device includes a plurality of discrete conductive features formed at the edge of an integrated circuit proximate a scribe line. The discrete conductive features may comprise a plurality of staggered lines, a plurality of horseshoe-shaped lines, or a combination of both.

Crack stop and moisture barrier

A method for generating or refining an OPC model for use in wafer fabrication. A predetermined feature layout is used to prepare a mask for use in, for example, a photolithographic process. The mask is used to create structures corresponding to mask features on a semiconductor wafer using the mask. Measurements of the actual mask features and wafer features may then be assessed and correlated, and the results used to generate an OPC model or refine an existing one. In addition, the OPC may be used to simulate a fabrication operation by applying the OPC tool to a predetermined layout to produce a mask image and a wafer image, and then comparing the predetermined layout to the simulated wafer image to determine at least one fitness value.

Method for OPC model generation

A method of preventing resist line collapse in damascene structures and a structure thereof is disclosed. A damascene pattern for resist lines is enhanced with ribs extending therefrom. The ribs provide mechanical support for resist lines and improve the lithography process for forming the resist lines, particularly when a negative focus is used. The ribs may extend between vias in an underlying material layer. The method results in structurally strong resist lines for damascene structures that are less likely to collapse.

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Hopewell Junction, NY, United States of America

O Seo Park