Samsung Electronics Co., Ltd.

O-Ik Kwon

Myeong-Cheol Kim

Dong-Chan Kim

Bum-Soo Kim

Jae-Ho Min

Yong-Woo Lee

Sang-sup Jeong

Jong-Chul Park

Han-Na Cho

Se-Hyeong Lee

Hye-Ji Yoon

A method of manufacturing an MRAM device including forming a first insulating interlayer and a lower electrode contact, the lower electrode contact extending through the first insulating interlayer; forming a lower electrode layer, a magnetic tunnel junction layer, an upper electrode layer, and a first hard mask layer on the first insulating interlayer and lower electrode contact; forming a second hard mask on the first hard mask layer; etching the first hard mask layer and upper electrode layer to form a first hard mask and upper electrode; forming a spacer on sidewalls of the upper electrode and hard masks; and etching the magnetic tunnel junction layer and the lower electrode layer to form a structure including a lower electrode and a magnetic tunnel junction pattern on the lower electrode contact, wherein a layer remains on the upper electrode after etching the magnetic tunnel junction layer and the lower electrode layer.

Method of manufacturing a magnetoresistive random access memory device using hard masks and spacers

Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

Methods of forming fine patterns in semiconductor devices

Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning, including respective mask pattern elements having different widths.

A method of forming a contact for a semiconductor device by forming a storage node contact in a semiconductor substrate having a first pad and a second pad formed thereon. The storage node contact is connected to the second pad. A bit line electrically insulated from the storage node contact by a spacer and electrically connected to the first pad.

Method of forming capacitor over bitline contact

Provided is a method for fabricating a stacked capacitor with improved vertical and bottom etching profiles without electrical bridge between adjacent lower electrodes. Conductive layer for a lower electrode is deposited over an insulating layer whose top portion is made of a nitride etching barrier layer. During the etching of the conductive layer and subsequent overetching for lower electrode pattern, the nitride etching barrier layer serves an etching stopper and allows easier formation of polymer buildups on sidewalls of the lower electrode, more particularly on a bottom edge thereof. Resulting polymer buildups serve to prevent unacceptable bottom and sidewall etching of the lower electrode.

Method for fabricating a DRAM cell capacitor including etching upper conductive layer with etching byproduct forming an etch barrier on the conductive pattern

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Sungnam-si, South Korea

O-Ik Kwon