Samsung Electronics Co., Ltd.

Nyun-Tae Kim

Ki-Hong Kim

Shu-Jiang Wang

Dae-Seung Jeong

Hwa-Su Koh

Ki-Mio Ueda

Young-Gyu Kang

Soon-Bok Jang

Mi-jeong Kim

Duck Hyun Chang

Kimio Ueda

The phase detection circuit may allow an operating speed of a semiconductor circuit to be increased irrespective of whether a combinational logic circuit within the semiconductor circuit operates at lower operating speeds. The phase detection circuit may adjust a data rate of an input data signal and selectively enable reference signals and error signals. The phase detection circuit may be included within a clock data recovery circuit.

Phase detection circuit and method thereof and clock recovery circuit and method thereof

A circuit for recovering a clock signal may include a frequency multiplier configured to generate a plurality of local clock signals, each having a different phase, based on a plurality of received global clock signals at a first frequency and each having a different phase. The local clock signals may be generated at a second frequency higher than the first frequency. The circuit may include a phase interpolator configured to generate a recovered clock signal at a given phase and at a third frequency, based on the generated local clock signals, and a phase shifter configured to adjust the phase of the recovered clock signal so as to synchronize the phase of the recovered clock signal with a phrase of input data that is input to the phase shifter.

Circuits and methods for recovering a clock signal

A quarter-rate clock recovery circuit includes a clock generator, a phase interpolation unit, a phase detector, and a controller. The clock generator generates first through fourth clocks having a quarter frequency of a data-rate of input data, the second, third and fourth clocks have phase differences of 90, 180, and 270 degrees with respect to a phase of the first clock, respectively. The phase interpolation unit performs a phase interpolation on the first through fourth clocks based on control signals to generate fifth through eighth clocks that have a quarter frequency of the data-rate of the input data, the fifth clock tracking a phase of the input data, the sixth, seventh, and eighth clocks respectively have phase differences of 45, 90, and 135 degree with respect to a phase of the fifth clock. The phase detector outputs signals corresponding to phase differences between the input data and the fifth through eighth clocks based on the input data and the fifth through eighth clocks. The controller generates the control signals to control the phase interpolation unit based on the signals output from the phase detector.

Quarter-rate clock recovery circuit and clock recovering method using the same

A level shifter and method thereof. The level shifter may include a protective circuit configured to receive an input signal having an input voltage level, the input signal received on an input line, the protective circuit reducing the input voltage level to generate a stabilized input signal and a first inverter configured to invert the stabilized input signal and to output an inverted output signal at an inverted output voltage level to a first node. In an example method, an input signal may be received at an input voltage level, the input voltage level may be reduced to output a stabilized input signal, the stabilized input signal may be inverted to output an inverted output signal at an inverted output voltage level to a first node and the first node may be transitioned to a node voltage level based on the input signal. The level shifter and method thereof may reduce a power consumption and/or a chip size of a semiconductor device.

Level shifter and method thereof

First and fourth phase difference signals, and first and second phase difference information signals respectively having first, fourth, second and third phase differences may be generated using an input signal and a plurality of clock signals each of which has different phase with each other. A level of the first phase difference information signal may be lowered, and a second phase difference signal having a first level less than levels of the first and fourth phase difference signals may be generated. A level of the second phase difference information signal may be lowered, and a third phase difference signal having a second level less than the levels of the first and fourth phase difference signals may be generated. The level of the phase difference signals having a phase difference lower than 45&#xb0; may be lowered, and thus the operational speed of a CDR device may be maintained and/or the jitter characteristics may be enhanced.

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Yongin-si, South Korea

Nyun-Tae Kim