Sun Microsystems, Inc.

Oracle International Corporation

Oracle America, Inc.

Isothermal Systems Research, Inc.

Nyles I Nettleton

Ashley N Saulsbury

Michael W Parkin

Howard Lee Davidson

David R Emberson

Bruce M Guenin

Earl T Cohen

James B Burr

Dawei Huang

Donald E Tilton

David S Allison

Thomas M McWilliams

Robert David Hopkins, Ii

Derek E Pappas

Liang T Chen

Jing Shi

Jeffrey B Rubin

Michael H S Dayringer

Jeffrey M Broughton

Oyekunle A Olukotun

Theresa Sze

Rick Lytel

Ii Robert David Hopkins

A chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. Moreover, surfaces of each of the semiconductor dies in the stepped terrace include two rows of first pads approximately parallel to edges of the semiconductor dies. Furthermore, the chip package includes a high-bandwidth ramp component, which is positioned approximately parallel to the terrace, and which has a surface that includes second pads arranged in at least two rows of second pads for each of the semiconductor dies. The second pads are electrically and mechanically coupled to the exposed first pads by connectors. Consequently, the electrical contacts in the chip package may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique.

Ramp-stack chip package with variable chip spacing

A base mechanism for use in a multi-chip module (MCM) is described. This base mechanism includes a substrate having top and bottom surfaces. The bottom surface includes first electrical connectors that convey power, and through-substrate vias (TSVs) between the top and bottom surfaces are electrically coupled to these electrical connectors. Furthermore, a bridge chip is rigidly mechanically coupled to the top surface. This bridge chip includes proximity communication connectors that communicate information via proximity communication with one or more island chips in the MCM. Additionally, spacers are rigidly mechanically coupled to the top surface of the substrate. In conjunction with the bridge chip, the spacers define cavities on the top surface, which include second electrical connectors. These second electrical connectors are electrically coupled to the TSVs, and communicate additional information with and convey power to the one or more island chips.

Base plate for use in a multi-chip module

One embodiment of the present invention provides an integrated circuit module. This module includes a semiconductor die with an active face, upon which active circuitry and signal pads reside, and a back face opposite the active face. The module uses a flexible cable to deliver electrical power to the active face of the semiconductor die from a power distribution board located above the active face of the semiconductor die. This flexible cable provides electrical power to the semiconductor die without interfering with the alignment and heat removal functions of the module.

Multi-chip module structure with power delivery using flexible cables

An electronics equipment heat exchanger system for thermally managing the electronic devices of a computer server and the exhaust air emitted from the computer server. The electronics equipment heat exchanger system generally includes a heat exchanger attached near an air outlet of a support unit for a support rack, a thermal management unit fluidly connected to the heat exchanger, and a thermal conditioning unit fluidly connected to the thermal management unit and the heat exchanger. The thermal management unit directly thermally manages one or more electronic devices of the server mainboard while the heat exchanger thermally manages the exhaust air before the exhaust air exits through the outlet of the support unit of the computer server.

Electronics equipment heat exchanger system

According to the invention, a processing core () comprising a processing pipeline () having N-number of processing paths (), each of which process instructions () on M-bit data words. In addition, the processing core () includes one or more register files (), each preferably having Q-number of registers which are M-bits wide. Preferably, one of the Q-number of registers in at least one of the register files () is a program counter register dedicated to hold a program counter, and one of the Q-number of registers in at least one of the register files is a zero register dedicated to hold a zero value. In this manner, program jumps can be executed by adding values to the program counter in the program counter register, and memory address values can be calculated by adding values to the program counter stored in the program counter register or to the zero value stored in the zero register.

VLIW computer processing architecture having the problem counter stored in a register file register

A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.

Method and apparatus for simulation processor

A novel processor chip ( ) having a processing core ( ), at least one bank of memory ( ), an I/O link ( ) configured to communicate with other like processor chips or compatible I/O devices, a memory controller ( ) in electrical communication with processing core ( ) and memory ( ), and a distributed shared memory controller ( ) in electrical communication with memory controller ( ) and I/O link ( ). Distributed shared memory controller ( ) is configured to control the exchange of data between processor chip ( ) and the other processor chips or I/O devices. In addition, memory controller ( ) is configured to receive memory requests from processing core ( ) and distributed shared memory controller ( ) and process the memory request with memory ( ). Processor chip ( ) may further comprise an external memory interface ( ) in electrical communication with memory controller ( ). External memory interface ( ) is configured to connect processor chip ( ) with external memory, such as DRAM. Memory controller ( ) is configured to receive memory requests from processing core ( ) and distributed shared memory controller ( ), determine whether the memory requests are directed to memory ( ) on chip ( ) or the external memory, and process the memory requests with memory ( ) on processor chip ( ) or with the external memory through external memory interface ( ).

VLIW computer processing architecture with on-chip dynamic RAM

An optical interconnect is provided that optically connects two adjacent printed circuit boards, or electrical component. The optical interconnect includes a floating frame which is flexibly connected to one electrical component. The floating frame includes a plurality of optical guides. The optical guides are connected to the electrical component either electronically or optically. A second frame, coupled to a second electrical component also contains a plurality of optical guides. A mechanical guide assembly positions the first frame and the second frame are optically coupled. The optical guide in the second frame connects to the second electrical component providing a path for a signal from the first electrical component to the second electrical component.

Optical interconnect

Growing community of inventors

Campbell, CA, United States of America

Nyles I Nettleton