Advanced Micro Devices Corporation

Nuwan S Jayasena

Shaizeen Dilawarhusen Aga

Gabriel H Loh

James Michael O'Connor

Yasuko Eckert

Michael Ignatowski

Michael J Schulte

Michael Mantor

Manish Arora

Alexander Dodd Breslow

Johnathan R Alsop

John Kalamatianos

Kevin John McGrath

Rex Eldon McCrary

Philip J Rogers

Sooraj Puthoor

Sebastien Nussbaum

Mark M Leather

Robert Scott Hartog

Lisa R Hsu

David Andrew Roberts

Ralph Clay Taylor

Thomas R Woller

Dong Ping Zhang

Bradford Michael Beckmann

Amin Farmahini-Farahani

Andrew Gregory Kegel

Srilatha Manne

Allen H Rush

Michael Warren Boyer

Ashwin Aji

Michael L Chu

Amin Farmahini Farahani

Muhammad Amber Hassaan

Yi Xu

Sudhanva Gurumurthi

William Lloyd Bircher

Alexandru Dutu

Madhu Saravana Sibi Govindan

Niladrish Chatterjee

Shrikanth Ganapathy

Yuan Xie

Mahzabeen Islam

Indrani Paul

Vilas K Sridharan

Jagadish B Kotra

Niti Madan

Mohamed Assem Abd ElMohsen Ibrahim

Reena Panda

Andrew McCrabb

Paula Aguilera Diez

Anirban Nag

Mauricio Breternitz, Jr

Anthony T Gutierrez

Mithuna Shamabhat Thottethodi

Arkaprava Basu

Onur Kayiran

Mitesh Ramesh Meswani

Jayanth Gummaraju

Nicholas P Malaya

Ralph Clayton Taylor

Ross Voigt La Fetra

Brandon K Potter

Georgios Mappouras

Jonathan Alsop

Suchita Pati

Andreas Prodromou

Hyojong Kim

Hyesoon Kim

Farzad Khorasani

Fused data generation and associated communication techniques are described. In an implementation, a system includes processing system having a plurality of processors. A data generation and communication tracking module is configured to track programmatically defined data generation and associated communication as performed by the plurality of processors. A targeted communication module is configured to trigger targeted communication of data between the plurality of processors based on the tracked programmatically defined data generation and associated communication.

Fused data generation and associated communication

Systems and techniques for data-driven precision memory access of cache block data are described. Computing system components are informed as to instances where access operations involve deducing a necessary precision of the data format and expressing the requested data in a lower-precision data format with minimal to no accuracy loss. In one example, executable code for a computational task includes hints that identify when memory requests involve accessing data in a numeric data format based on a deduced precision of the stored data during memory access. The described techniques thus overcome conventional drawbacks facing systems that transmit and compute data in a higher-precision data format than required by the stored values.

Data-driven precision for memory access

Programmable data storage memory hierarchy techniques are described. In one example, a data storage system includes a memory hierarchy and a data movement controller. The memory hierarchy includes a hierarchical arrangement of a plurality of memory buffers. The data movement controller is configured to receive a data movement command and control data movement between the plurality of memory buffers based on the data movement command.

Programmable data storage memory hierarchy

Modifying memory page attributes using a programmable page attribute register of a core executing a process is described. In accordance with the described techniques, a host includes a core that is configured to generate a modified page table attribute for a page in system memory. The modified page table attribute represents at least one demoted permission for a page as specified by a system page table. The core is configured to maintain the modified page table attribute locally in the programmable page attribute register and execute at least one operation allocated to the page according to the modified page table attribute.

Memory page attribute modification

Resource access control is described. In accordance with the described techniques, a process (e.g., an application process, a system process, etc.) issues an instruction seeking access to a computation resource (e.g., a processor resource, a memory resource, etc.) to perform a computation task. An execution context for the instruction is checked to determine whether the execution context includes a resource indicator indicating permission to access the processor resource. Alternatively or additionally, the instruction is checked against an access table which identifies processes that are permitted and/or not permitted to access the computation resource.

Resource access control

Process isolation for a PIM device through exclusive locking includes receiving, from a process, a call requesting ownership of a PIM device. The request includes one or more PIM configuration parameters. The exclusive locking technique also includes granting the process ownership of the PIM device responsive to determining that ownership is available. The PIM device is configured according to the PIM configuration parameters.

Process isolation for a processor-in-memory ('PIM') device

An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.

Memory system with region-specific memory access scheduling

Methods and apparatuses to control digital data transfer via a memory channel between a memory module and a processor are disclosed. At least one of the memory module or the processor coalesces a plurality of short data words into multicast coalesced block data comprising a single data block for transfer via the memory channel. Each of the plurality of short data words pertains to one of at least two partitioned memory submodules in the memory module. The multicast coalesced block data is communicated over the memory channel.

System and method for coalesced multicast data transfers over memory interfaces

An approach is provided for processing near-memory processing commands, e.g., PIM commands, using PIM register definition data that defines multiple combinations of source and/or destination registers to be used to process PIM commands. A particular combination of source and/or destination registers to be used to process a PIM command is specified by the PIM command or determined by a near-memory processing element processing the PIM command. According to another implementation, the PIM register definition data specifies an initial combination of source and/or destination registers and one or more update functions for each PIM command. A near-memory processing element processes a PIM command using the initial combination of source and/or destination registers and uses the one or more update functions to update the combination of source and/or destination registers to be used the next time the PIM command is processed.

Approach for processing near-memory processing commands using near-memory register definition data

Near-memory compute elements perform memory operations and temporarily store at least a portion of address information for the memory operations in local storage. A broadcast memory command is then issued to the near-memory compute elements that causes the near-memory compute elements to perform a subsequent memory operation using their respective address information stored in the local storage. This allows a single broadcast memory command to be used to perform memory operations across multiple memory elements, such as DRAM banks, using bank-specific address information. In one implementation, the approach is used to process workloads with irregular updates to memory while consuming less command bus bandwidth than conventional approaches. Implementations include using conditional flags to selectively designate address information in local storage that is to be processed with the broadcast memory command.

Approach for performing efficient memory operations using near-memory compute elements

In accordance with the described techniques for bank-level parallelism for processing in memory, a plurality of commands are received for execution by a processing in memory component embedded in a memory. The memory includes a first bank and a second bank. The plurality of commands include a first stream of commands which cause the processing in memory component to perform operations that access the first bank and a second stream of commands which cause the processing in memory component to perform operations that access the second bank. A next row of the first bank that is to be accessed by the processing in memory component is identified. Further, a precharge command is scheduled to close a first row of the first bank and an activate command is scheduled to open the next row of the first bank in parallel with execution of the second stream of commands.

Bank-level parallelism for processing in memory

An apparatus includes a memory controller that includes logic to receive a first memory request having a first request type and a second memory request having a second request type. The apparatus also includes a scheduling unit that includes logic to schedule an order of the first and second memory requests for execution based upon a first parameter value and a second parameter value. The first parameter value corresponds to a utility and energy cost for the first memory request and the second parameter value corresponds to a utility and energy cost for the second memory request.

Allocation of resources when processing at memory level through memory request scheduling

Predicates for processing in memory is described. In accordance with the described techniques, a predicate instruction to compute a conditional value based on data stored in a memory is provided to a processing-in-memory component. A response that includes the conditional value computed by the processing-in-memory component is received, and the conditional value is stored in a predicate register. One or more conditional instructions are provided to the processing-in-memory component based on the conditional value stored in the predicate register.

Predicates for processing-in-memory

Adaptive scheduling of memory requests and processing-in-memory requests is described. In accordance with the described techniques, a memory controller receives a plurality of processing-in-memory requests and a plurality of non-processing-in-memory requests from a host. The memory controller schedules an order of execution for the plurality of processing-in-memory requests and the plurality of non-processing-in-memory requests based at least in part on a processing-in-memory request stall threshold and a non-processing-in-memory request stall threshold. In response to a system switching (e.g., from executing processing-in-memory requests to executing non-processing-in-memory requests or from executing non-processing-in-memory requests to executing processing-in-memory requests), the memory controller modifies the processing-in-memory request stall threshold and the non-processing-in-memory request stall threshold. The memory controller continues scheduling an order of execution for subsequent requests received from the host using the modified stall thresholds.

Adaptive scheduling of memory and processing-in-memory requests

A processing device including a plurality of clusters of processor cores and a method for use in the processing device is disclosed. Each processor core in a cluster of processor cores is in communication with the other processor cores in the cluster and at least one processor core of each cluster is in communication with at least a processor core of a different cluster of processor cores. Each processor core is configured to store a product of a portion of a first matrix and a first portion of a second matrix in the memory, and store a product of the portion of the first matrix and a second portion of the second matrix in the memory, where the second portion of the second matrix is received from a processor core in the cluster of processor cores.

Device and method for accelerating matrix multiply operations

Growing community of inventors

Santa Clara, CA, United States of America

Nuwan S Jayasena