Seagate Technology Incorporated

Nurul Amin

Insik Jin

Song Sheng Xue

Wei Tian

Ming Sun

Sining Mao

Venugopalan Vaithyanathan

Patrick Joseph Ryan

John Bortins

Ying D Yan

Beat G Keel

Youngpil Kim

Johannes Van Ek

Steven Kalderon

Shaoping Li

Wayne Allen Bonin

Hans L Leuthold

Chulmin Jung

John Robert Pendray

Young Pil Kim

Andrew D White

Bradley Jay Ver Meer

Yuming Zhou

Roger L Hipwell

Zheng Gao

Kaizhong Gao

Mark Thomas Kief

Dadi Setiadi

Michael Xuefei Tang

Edward Stephens Murdock

Venkatram Venkatasamy

Richard P Michel

Philip George Pitcher

Anthony M Mack

Uri Cohen

Lance Eugene Stover

Taras Grigorievich Pokhil

Gregory S Mowry

Dian Song

Eric Shane Linville

Ibro Tabakovic

Ned Tabat

Richard P Larson

Martin Louis Plumer

Jeffery K Berkowitz

Menachem Rafaelof

Steven Paul Bozeman

Nathan Curland

Andrew James Wirebaugh

Venu Vaithyanathan

Insik Jim

Tim Madsen

Michael Allen Seigler

Dimitar Velikov Dimitrov

Haiwen Xi

Yong Lu

Hai Li

Sakhrat Khizroev

Olle Gunnar Heinonen

Michael Thomas Johnson

Alexander Mikhailovich Shukh

Robert Earl Rottmayer

Dmitri Litvinov

Ladislav Rudolf Pust

Hao Fang

Charles H Tolman

Stefan Andrei Ionescu

Feng Y Wang

Pu-Ling Lu

Andrzej Adam Stankiewicz

Taras Grigoryevich Pokhil

Vee Sochivy Kong

Alan Biggar Johnston

Jumna P Ramdular

Sunita B Gangopadhyay

Bill Crue

Daniel John Brown

James H Giusti

Janusz Jozef Nowak

Michael R Montemorra

Wei Tan

Paul A Jallen

Alan B Johnston

Rick Michel

Ananth Naman

Charles Joseph Olson

Timothy Radke

Jin Li

Andrew Wirebaugh

Programmable metallization memory cells having an active electrode, an opposing inert electrode and a variable resistive element separating the active electrode from the inert electrode. The variable resistive element includes a plurality of alternating solid electrolyte layers and electrically conductive layers. The electrically conductive layers electrically couple the active electrode to the inert electrode in a programmable metallization memory cell. Methods to form the same are also disclosed.

Programmable metallization memory cell with layered solid electrolyte structure

An apparatus and associated method for a multi-bit memory capable of being selected with a magnetic layer. Various embodiments of the present invention are generally directed to a first selection layer with a low coercivity that is disposed between first and second storage layers that each have a high coercivity. In response to magnetic saturation of the first selection layer, programming of a logical state to the second storage layer is allowed.

Multi-bit memory with selectable magnetic layer

An electronic device that includes a first programmable metallization cell (PMC) that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode; and a second PMC that includes an active electrode; an inert electrode; and a solid electrolyte layer disposed between the active electrode and the inert electrode, wherein the first and second PMCs are electrically connected in anti-parallel.

Programmable metallization cell switch and memory units containing the same

Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode.

Method of forming a programmable metallization memory cell

A method of fabricating a discrete track magnetic recording media. A base layer is provided onto which repeating and alternating magnetic layer and non-magnetic layers are deposited. The thickness of the magnetic layer corresponds to the width of the track of the recording media. A cylindrical rod can be used as the base layer, such that the alternating magnetic and non-magnetic layers spiraling or concentric layers around the rod. The resulting media layer can be cut or sliced into individual magnetic media or used to imprint other media discs with the discrete pattern of the media layer.

Discrete track media

A method of fabricating a recording head includes depositing an insulator material onto at least a portion of a first member, wherein the insulator material forms an insulator film having a film thickness. The method further includes depositing a writer pole material onto the insulator film, wherein the writer pole material forms a writer pole member, and wherein the insulator film is between the writer pole member and a contact layer. Further, in some embodiments, the film thickness determines the distance between the writer pole member and the first contact member and also determines the distance between the writer pole member and the second contact member.

Method of manufacturing a magnetic head

A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a programmable unipolar resistive sense switching element. The memory element is programmed to a selected resistance state by application of a selected write current in a selected direction through the cell, wherein a first resistance level is programmed by passage of a write current in a first direction and wherein a second resistance level is programmed by passage of a write current in an opposing second direction. The switching element is programmed to a selected resistance level to facilitate access to the selected resistance state of the memory element.

Non-volatile memory cell with programmable unipolar switching element

Programmable resistive memory cell with oxide layer

A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

Schottky diode switch and memory units containing the same

A non-volatile memory cell and method of use thereof. In some embodiments, an individually programmable resistive sense memory (RSM) element is connected in series with a programmable metallization cell (PMC) switching element. In operation, while the switching element is programmed to a first resistive state, no current passes through the RSM element and while a second resistive state is programmed to the RSM element, current passes through the RSM element.

Non-volatile memory cell stack with dual resistive elements

An anti-parallel diode structure and method of fabrication is presently disclosed. In some embodiments, an anti-parallel diode structure has a semiconductor region comprising a first insulator layer disposed between a first semiconductor layer and a second semiconductor layer. The semiconductor region can be bound on a first side by a first metal material and bound on a second side by a second metal material so that current below a predetermined value is prevented from passing through the semiconductor region and current above the predetermined value passes through the semiconductor region.

Anti-parallel diode structure and method of fabrication

An apparatus and associated method for a non-volatile memory cell, such as a multi-bit magnetic random access memory cell. In accordance with various embodiments, a first magnetic tunnel junction (MTJ) is adjacent to a second MTJ having a magnetic filter. The first MTJ is programmed to a first logical state with a first magnetic flux while the magnetic filter absorbs the first magnetic flux to prevent the second MTJ from being programmed.

Flux programmed multi-bit magnetic memory

Growing community of inventors

Woodbury, MN, United States of America

Nurul Amin