Sony Corporation

Nozomu Takatori

Takahisa Ueno

Yasuaki Hisamatsu

Junichi Inutsuka

Yuichiro Araki

Tomohiro Takahashi

Hiroki Ui

Kenichi Okumura

Noriya Maeda

Hideo Nakayama

Junichi Iutsuka

An integrating A/D converter includes: a comparator comparing an input voltage to a reference voltage having a ramp waveform, a voltage value of which linearly varies with time; a higher-order bit counter starting operation or stopping operation triggered by inversion of an output signal of the comparator and outputting higher order bits by performing counting in a cycle of a clock signal; and a time-to-digital converter latching phase information of the clock signal corresponding to plural signals obtained by delaying an output signal of the comparator and decoding the latched values to output lower order bits having higher resolution than the clock cycle.

Integrating A/D converter, integrating A/D conversion method, solid-state imaging device and camera system

A solid-state imaging including a comparing circuit, an inverting circuit, and a masking circuit, and that performs column parallel AD conversion processing of analog pixel signals output from a plurality of pixels arranged in a two-dimensional matrix form. The comparing circuit outputs a difference signal obtained by comparing each of the pixel signals outputted from the pixels with a reference signal having a ramp waveform. The inverting circuit inverts a logic of the difference signal outputted from the comparing circuit. The masking circuit masks an output of an output signal of the inverting circuit to a circuit in a subsequent stage during an input offset canceling period in which the comparing circuit cancels an input offset between the pixel signal and the reference signal.

Solid-state imaging device, driving control method thereof, and imaging apparatus

A solid-state imaging includes a comparing circuit, an inverting circuit, and a masking circuit, and performs column parallel AD conversion processing of analog pixel signals outputted from a plurality of pixels arranged in a two-dimensional matrix form. The comparing circuit outputs a difference signal obtained by comparing each of the pixel signals outputted from the pixels with a reference signal having a ramp waveform. The inverting circuit inverts a logic of the difference signal outputted from the comparing circuit. The masking circuit masks an output of an output signal of the inverting circuit to a circuit in a subsequent stage during an input offset canceling period in which the comparing circuit is canceling an input offset between the pixel signal and the reference signal.

A solid-state imaging device includes a pixel array unit configured by arranging plural unit pixels including charge generating units and output transistors that output processing object signals corresponding to charges generated by the charge generating units, an imaging-condition determining unit that determines whether a large light-amount imaging condition, when an amount of light larger than that of light representing a saturation level is made incident on the charge generating units, is satisfied, and a control unit that performs control, on condition that the imaging-condition determining unit determines that the large light-amount imaging condition is satisfied, to correct an output signal based on processing object signals outputted from the unit pixels such that a harmful effect due to the large light-amount imaging condition is suppressed in the output signal.

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Nagasaki, Japan

Nozomu Takatori