Unisantis Electronics Singapore Pte. Ltd.

Nozomu Harada

Fujio Masuoka

Koji Sakui

Masakazu Kakumu

Hiroki Nakamura

Yisuo Li

Zhixian Chen

Xinpeng Wang

Riichiro Shirota

Aashit Ramachandra Kamath

Yoshiaki Kikuchi

Navab Singh

Patrick Guo-Qiang Lo

Teng Soong Phua

Zheng Tao

Xiang Li

Kenichi Kanazawa

Yoshihisa Iwata

Phillipe Matagne

Min Soo Kim

Players which entirely cover top parts of Si pillars and which surround the Si pillars at equal widths in a plan view are formed by self-alignment with the Si pillars, W layers are formed on the Players, a band-shaped contact hole which is in contact with respective partial regions of the W layers and which extends in the Y direction is formed, and a supply wiring metal layer is formed by filling the band-shaped contact hole. The partial regions of the W layers are shaped so as to protrude to outside of the band-shaped contact hole in a plan view.

Manufacturing method of pillar-shaped semiconductor device

A semiconductor element memory device includes a first block including first memory cells arranged in a matrix, and/or a second block including second memory cells each formed of two memory cells. The memory device is configured to perform a data hold operation of controlling voltages to be applied to plate lines, word lines, a source line, odd-numbered bit lines, and even-numbered bit lines to hold, in a semiconductor base, a positive hole group generated by an impact ionization phenomenon or a gate-induced drain leakage current, and a data erase operation of controlling voltages to be applied to the plate lines, the word lines, the source line, the odd-numbered bit lines, and the even-numbered bit lines to discharge the positive hole group from the semiconductor base. The number of first blocks and the number of second blocks are variable in the memory device that is in operation.

Memory device having a matrix of SGT memory cells

On P layer bases extending in a band shape in a first direction in plan view, Nlayers also extending in a band shape in the first direction and Si pillars are formed. Subsequently, a gate insulating layer and gate conductor layers are formed so as to surround the Si pillars. Subsequently, contact holes whose bottom portions are in contact with the Nlayers are formed in an insulating layer, and first conductor W layers are formed at the bottom portions of the contact holes. Subsequently, insulating layers each having a hole are formed in the contact holes. Subsequently, a second conductor W layer is formed in a second direction perpendicular to the first direction so as to be connected to the gate conductor layers.

Memory device including pillar-shaped semiconductor element and method for manufacturing the same

A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, the first and second impurity regions and first and second gate conductor layers are connected to source, bit, word, and plate lines respectively, and a page read operation includes a first refresh operation of increasing by an impact ionization phenomenon, a group of positive holes in the semiconductor body of a memory cell for which page writing has been performed and a subsequent second refresh operation of making some of a group of positive holes in the semiconductor body of a memory cell for which page writing has not been performed disappear and decreasing the number of positive holes.

Memory device with stacked body orthogonal to substrate and method using write and ease page refresh operations

On a semiconductor base that extends in a band shape in a direction (first direction) perpendicular to a line X-X' direction (second direction) in plan view, an Nlayer, a Player, and Si pillars that also extend in a band shape in the first direction are formed. Subsequently, a gate insulating layer and gate conductor layers are formed so as to surround the Si pillars. Subsequently, a contact hole whose bottom portion is in contact with the Nlayer and the Player is formed in an insulating layer, and a first conductor W layer is formed at the bottom portion of the contact hole. Subsequently, an insulating layer that has a hole is formed in the contact hole. Subsequently, a second conductor W layer is formed in the line X-X′ direction so as to be connected to the gate conductor layers.

Pillar-shaped semiconductor device and method for manufacturing the same

Provided is a semiconductor device including a memory cell and a MOS transistor. The memory cell includes a first gate insulating layer and a first gate conductor layer surrounding a first pillar-shaped p layer erected on a first p layer substrate, and a second gate insulating layer, a second gate conductor layer, and Nlayers surrounding a second pillar-shaped p layer connected to the first pillar-shaped p layer. The MOS transistor includes a third pillar-shaped p layer erected on a second p layer substrate connected to the first p layer substrate, and a third gate insulating layer, a third gate conductor layer, and Nlayers surrounding a fourth pillar-shaped p layer placed on and in contact with the third pillar-shaped p layer. In a vertical direction, the second pillar-shaped p layer has a length shorter than a length of the fourth pillar-shaped p layer.

Semiconductor device including memory element

By controlling voltages applied to plate lines, word lines, source lines, and bit lines, a memory device that uses semiconductor elements performs a data retention operation of holding positive hole groups formed by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base material, and a memory erase operation of removing positive hole groups from inside the semiconductor base material. The memory device also performs a data erase operation during the memory erase operation to remove positive hole groups from inside the semiconductor base material of all the memory cells in a block made up of the memory cells, which are arrayed in a matrix.

Semiconductor element memory cell and semiconductor element memory device

A memory device is formed with at least one memory array, the memory array being formed with a plurality of pages and a plurality of bit lines, each page being formed with a plurality of memory cells arranged in a row direction on a substrate in a plan view, the plurality of memory cells being connected to the bit lines disposed in a column direction. Each of the memory cells included in each of the pages includes a semiconductor base material, a first impurity region and a second impurity region positioned in respective ends of the semiconductor base material, a first gate conductor layer, and a second gate conductor layer. In the memory cell, the first impurity region is connected to a source line, the second impurity region is connected to a bit line, one of the first and second gate conductor layers is connected to a word line, and the other is connected to a plate line. A page erase operation, a page write operation, and a page read operation are performed by controlling a voltage applied to each of the source line, the bit line, the word line, and the plate line. At least one of the bit lines and one of the pages are selected in the page erase operation, the page write operation, and the page read operation, and an erase operation on the memory cell connected to both the bit line and the page thus selected, a write operation of storage data of the sense amplifier circuit to the memory cell, or a read operation from the memory cell to the sense amplifier circuit is executed.

Memory device including semiconductor element

Si bodiestoto, andtoare disposed parallel to a substrateand are adjacent to each other in a horizontal direction at regular intervals. A HfOlayersurrounds the Si bodiesto. TiN layerstosurround the HfOlayer, are isolated from each other, and are each formed of portions contiguous in the horizontal direction. The Si bodiestoare formed stepwise in cross-sectional view in the terminating end in the horizontal direction. Metal wiring layerstoare connected to the TiN layerstoand extend up to above an insulating layerthrough contact holestoextending in a vertical direction from the terminating ends of the TiN layersto. The metal wiring layerstoare connected to word lines WLto WL

Semiconductor-element-including memory device

A semiconductor element memory device is configured to perform a data hold operation of controlling voltages to be applied to a plate line, a word line, a source line, and a bit line to hold, in a semiconductor base, a positive hole group formed by an impact ionization phenomenon or a gate-induced drain leakage current, and a data erase operation of controlling voltages to be applied to the plate line, the word line, the source line, and the bit line to discharge the positive hole group from the semiconductor base. The semiconductor element memory device includes a plurality of memory cells arranged in a matrix within a block, and constantly manages, using a controller circuit and a logical/physical conversion table, which physical block address of a dynamic flash memory corresponds to data stored in a logical block address.

Semiconductor element memory device

A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions, connected to a source line and a bit line, respectively, at both ends of the semiconductor base, and first and second gate conductor layers, one of which is connected to a word line and the other of which is connected to a plate line. A continuous operation of a page erase operation and a page write operation is performed by controlling voltages applied to the source line, the bit line, the word line, and the plate line without performing a reset operation for returning the voltage applied to the plate line to a ground voltage.

Memory device using semiconductor element

A data retention operation of holding positive hole groups generated by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base body is performed by controlling voltages applied to plate lines, word lines, a source line, odd-numbered bit lines, and even-numbered bit lines; and a data erase operation is performed by removing positive hole groups from inside the semiconductor base body by controlling the voltages applied to plate lines, word lines, source line, odd-numbered bit lines, and even-numbered bit lines and lowering a voltage of The semiconductor base body by means of capacitive coupling between the plate lines and word lines. A block is made up of memory cells arrayed in a matrix, and storage data is read from the memory cells in the block alternately to the odd-numbered bit lines and even-numbered bit line.

A memory device includes a page constituted by multiple memory cells arranged in a row form on a substrate, and performs a page write operation of controlling voltages to be applied to first and second gate conductor layers and first and second impurity layers of each memory cell included in the page to hold a positive hole group formed by an impact ionization phenomenon inside a channel semiconductor layer; During a page read operation, page data of a memory cell group selected with the word line is read to the sense amplifier circuit, and a refresh operation is performed at least once before the page read operation to hold a positive hole group formed by an impact ionization phenomenon inside a channel semiconductor layer.

Memory device using dynamic flash memory cells

A memory device includes a plurality of pages arrayed in a column direction in a plan view, each page being constituted by a plurality of memory cells arrayed in a row direction on a substrate. Each of the memory cells included in each of the pages includes a semiconductor base material, first and second impurity regions positioned at respective ends of the semiconductor base material, first, second, and third gate conductor layers. The first and second impurity regions, the first, second, and third gate conductor layers are connected to a source line, a bit line, a first select gate line, a plate line, and a second select gate line, respectively. Upon operation end of page write operation and page read operation, voltage of the plate line is set to negative voltage lower than 0 V through capacitive coupling of the plate line and each of the first and second select gate lines to improve data retention characteristics of a write memory cell.

A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions, connected to a source line and a bit line, respectively, at both ends of the semiconductor base, and first and second gate conductor layers, one of which is connected to a word line and the other of which is connected to a plate line. Page erase, page write, and read operations are performed by controlling voltages applied to the source, bit, word, and plate lines. A first operation of outputting data of a first page to an input/output circuit via a sense amplifier circuit and a second operation of reading data of a second page of the same bank as the first page to the bit line are performed in parallel.

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Tokyo, Japan

Nozomu Harada