Kabushiki Kaisha Toshiba

Nozomi Kasai

Takamichi Kasai

Takuya Fujimoto

Yoshiharu Hirata

A semiconductor memory device includes memory cells, write bit lines, read bit lines, latch circuits, a n-channel MOS transistor, and voltage setting circuits. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate. The first MOS transistors are connected commonly to the write bit lines and read bit lines. The latch circuits are provided for the write bit lines and hold write data for the memory cells. The n-channel MOS transistor transfer '1' data to the latch circuits in a data latch operation. The voltage setting circuits supply a potential corresponding to '0' data to the write bit lines in a read operation. In a data latch operation, the latch circuit corresponding to the write bit line connected to the memory cell into which &#x201c;0&#x201d; data is to be written latches the potential supplied to the write bit lines in a read operation.

Semiconductor memory device with MOS transistors, each including a floating gate and a control gate, a control method thereof, and a memory card including the same

This invention provides a nonvolatile semiconductor memory device capable of avoiding complicatedness of algorithm for normal write operation and a write operation prior to erasing in a memory system in which the distribution of threshold of cells after erasing is adjusted. This nonvolatile semiconductor memory device generates check bits as error correction code according to a check bit generating matrix so formed that in both the normal write operation and the write operation prior to erasing, the factors of &ldquo;1&rdquo; of respective rows satisfy the quantity absolutely necessary for generating check bits and the quantity of the factors of &ldquo;1&rdquo; is an odd number.

Error correcting circuit for making efficient error correction, and involatile semiconductor memory device incorporating the same error correcting circuit

The invention provides a flash memory having a security function and a protect function. When the release of the security function has been instructed, all data stored in each block of a flash memory main body is forcibly erased, ignoring the setting of the protect function. After that, the security function is released, thereby enabling readout of data. This being so, even if a third person releases the security function, leakage of data to the outside can be prevented.

Growing community of inventors

Kawasaki, Japan

Nozomi Kasai