Texas Instruments Corporation

Nozar Hassanzadeh

William P Stearns

Navinchandra Kalidas

Michael A Lamson

Hall E Jarman

A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a substrate having top and bottom surfaces with a plurality of rows and columns of vias extending therethrough from the top surface to the bottom surface and having a solder ball secured at the bottom surface to each via. A plurality of pairs of traces is provided on the top surface, each trace of each pair of traces extending to a different one of the vias and extending to vias on a plurality of the rows and columns, each of the traces of each pair being spaced from the other trace by a ball pitch, being maximized for identity in length and being maximized for parallelism and spacing. Each of the traces of a pair is preferably be further maximized for identity in cross-sectional geometry. A differential signal pair is preferably applied to at least one of a pair of traces. The layout can further include a further surface between the top and bottom surfaces insulated from the top and bottom surfaces, a plurality of the traces being disposed on the further surface.

Optimized circuit design layout for high performance ball grid array packages

A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a substrate having top and bottom surfaces with a plurality of rows and columns of vias extending therethrough from the top surface to the bottom surface and having a solder ball secured at the surface of each via. A plurality of pairs of traces is provided on the top surface, each trace of each pair of traces extending to a different one of the vias and extending to vias on a plurality of rows and columns, each of the traces of each pair being spaced from the other trace by a ball pitch, being maximized for identity in length and being maximized for parallelism and spacing. Each of the traces of a pair is preferably further maximized for identity in cross-sectional geometry. A differential signal pair is preferably applied to at least one of a pair of traces. The layout can further include a further surface between the top and bottom surfaces insulated from the top and bottom surfaces, a plurality of the traces being disposed on the further surface.

A structure ( ) is provided that is fabricated as a ball grid array substrate that includes a substrate dielectric ( ), a power ring ( ), a ground ring ( ), a plurality of traces, and a second metal layer ( ). The substrate dielectric ( ) includes a first side, a second side, and a cavity formed therein. The power ring ( ), the ground ring ( ), and the plurality of traces are provided on the first side of the substrate dielectric ( ). The plurality of traces, for example, may include a signal connection ( ), a ground connection ( ), and a power connection ( ). The second metal layer ( ) is provided on the second side of the substrate dielectric ( ) and is electrically coupled to the first side. For example, the second metal layer ( ) may serve as an active ground plane and electrically couple to a variety of ground connections, such as the ground connection ( ), and the ground ring ( ) through vias in the substrate dielectric ( ). The present invention also provides a method for forming a ball grid array package using the structure ( ).

Ball grid array package and method using enhanced power and ground distribution circuitry

A structure (10) is provided that is fabricated as a ball grid array substrate that includes a substrate dielectric (14), a power ring (18), a ground ring (20), a plurality of traces, and a second metal layer (16). The substrate dielectric (14) includes a first side, a second side, and a cavity formed therein. The power ring (18), the ground ring (20), and the plurality of traces are provided on the first side of the substrate dielectric (14). The plurality of traces, for example, may include a signal connection (22), a ground connection (24), and a power connection (26). The second metal layer (16) is provided on the second side of the substrate dielectric (14) and is electrically coupled to the first side. For example, the second metal layer (16) may serve as an active ground plane and electrically couple to a variety of ground connections, such as the ground connection (24), and the ground ring (20) through vias in the substrate dielectric (14). The present invention also provides a method for forming a ball grid array package using the structure (10).

Ball grid array package and method using enhanced power and ground

A semiconductor package includes a stiffener strip (10) having a die pad (18) and a body portion (12). A first surface (4) of the die pad (18) is offset from a second surface (3) of the body portion (12) a predetermined amount. The stiffener strip (10) includes an internal edge (27) concentrically disposed about the die pad (18) and tie straps (16) connecting the internal edge (27) to the die pad (18). A die (28) is affixed to the first surface (4) of the die pad (18). A substrate (20) has a first surface (17) and a second surface (19), with the second surface (19) being affixed to the first surface (2) of the body portion (12). The substrate (20) includes a window (22) and conductive elements (24). A plastic molding material (33) encompasses the die (28), at least a portion of the stiffener strip (10), and at least a portion of the substrate (20).

Semiconductor package with offset die pad

A ball grid array package (10) is provided that includes a heat spreader (14), a stiffener (13), a substrate (16), and a die or chip (12). The stiffener (13) is mounted to the heat spreader (14) and has a cavity formed therein. The stiffener (13) may serve as either a ground plane or a power plane of ball grid array package (10), depending on the desired implementation. The substrate (16) includes a signal plane (30) and a power bus (28) on a first surface and has a cavity formed therein. The substrate (16) is mounted to the stiffener (13) through a second surface. The substrate (16) further having at least one hole formed from the first surface to the second surface and a plurality of solder balls, similar to solder ball (20), to provide an external connection to the ball grid array package (10). Finally, the chip (12) is mounted to portion of the heat spreader (14) exposed through the cavity of the substrate (16) and the stiffener (13) and wire bonded to the various electrical planes, including the stiffener (13). The present invention also provides a method (100) for forming the ball grid array package (10) of the present invention.

Ball grid array package

A ball grid array package (62) having a deformable metal layer (20) is provided that includes a heat spreader (60), a stiffener (40) having a cavity and mounted to the heat spreader (60), a substrate (22), and a die (50). The substrate (22) includes a dielectric layer (10) with a cavity and cut-outs, the deformable metal layer (20), and a plurality of electrical traces for connection to solder balls. The dielectric layer (10) couples to the stiffener (40) through a second side and to the deformable metal layer (20) through the first side. The deformable metal layer (20) includes a cavity, a power ring (26), a ground ring (24), and a plurality of traces serving as either a ground connection, a signal connection, or a power connection for coupling with the plurality of solder balls. The deformable metal layer (20) also has a plurality of deformable metal layer portions each partially positioned over one of the cut-outs in the dielectric layer (10) and electrically coupled to the stiffener (40) through the cut-out. Each of the plurality of deformable metal layer portions also couples with one or more of the plurality of traces. The die (50) is mounted to the heat spreader (60) through the cavity of the substrate (22) and the stiffener (40). The present invention also provides a method for forming the ball grid array package (62).

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Plano, TX, United States of America

Nozar Hassanzadeh