Samsung Electronics Co., Ltd.

Noyoung Chung

Akio Misaka

Sang-Hwa Lee

Sanghwa Lee

Woonhyuk Choi

Taekyum Kim

Byung Je Jung

Youngseok Kim

Changsoo Kim

Sunghun Jung

Wooseok Kim

Jongdoo Kim

Myungsoo Noh

Dawoon Choi

Woojeong Shin

Hyejin Shin

Changmin Park

Narae Bang

Gyeong Seop Kim

Wonjoo Im

Hyunyong Jeong

A semiconductor device includes a logic cell on a substrate and a first metal layer on the logic cell. The first metal layer includes first and second power lines that extend in a first direction, and first, second, and third lower interconnection lines, which are respectively disposed on first, second, and third interconnection tracks defined between the first and second power lines that extend in the first direction parallel to each other. The first lower interconnection line includes first and second interconnection lines spaced apart from each other by a first distance, and the third lower interconnection line includes third and fourth interconnection lines spaced apart from each other by a second distance. The first and third interconnection lines have first and second ends, respectively, which face the second and fourth interconnection lines, respectively, and have different curvatures.

Semiconductor devices and methods of fabricating the same

A layout method of a semiconductor chip, includes designing a layout using a restriction rule such that a layout pattern having a length smaller than a first length in a first direction has to have a length smaller than a second length in a second direction, the second direction intersecting the first direction, generating a plurality of unit regions by partitioning the layout in the first direction, generating a plurality of target regions by adding a reference region to a partitioned edge of each of the plurality of unit regions, retargeting the plurality of target regions in parallel, and generating a correction layout by merging the plurality of retargeted target regions.

Layout method of semiconductor chip, semiconductor chip manufacturing method and computing device using same

A method of manufacturing a semiconductor chip includes designing a layout for a semiconductor chip, performing an optical proximity correction (OPC) on the layout, manufacturing a mask after performing the OPC, and manufacturing the semiconductor chip using the mask, wherein a plurality of OPC shapes corresponding to a rectangular pattern of the mask are included in the mask and at least one of the plurality of OPC shapes includes a multi-edge corner rounding OPC shape.

Optical proximity correction method, mask manufacturing method and semiconductor chip manufacturing method using the same

Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a logic cell on a substrate, and a first metal layer on the logic cell. The first metal layer includes first and second power lines and first to third lower lines on first to third wiring tracks therebetween. The first to third wiring tracks extend in parallel in the first direction. The first lower line includes first and second lines spaced apart in the first direction from each other at a first distance. The third lower line includes third and fourth lines spaced apart in the first direction at a second distance. The first line has a first end facing the second line. The third line has a second end facing the fourth line. A curvature at the first end is substantially the same as that at the second end.

Semiconductor device and method of fabricating the same

A method includes grouping, in a first layout, pattern regions which have duplicate layout patterns including weak regions as a group, calculating defect probabilities of the pattern regions, respectively, calculating a defect frequency and a defect rate of the group based on the defect probabilities of the pattern regions, predicting a degree of defects of a second layout of the pattern regions, based on the defect frequency and the defect rate, and performing an extreme ultraviolet (EUV) lithography process on a substrate, based on the second layout. The defect probabilities are calculated by performing an optical proximity correction (OPC) simulation on the pattern region, calculating a stochastic variation of a linewidth of a simulation pattern in the weak region as a Gaussian distribution, and defining a threshold linewidth, which is used as a reference of the random defect, in the Gaussian distribution.

Lithography and method of fabricating semiconductor device using the same

A method of manufacturing a semiconductor device is disclosed. The method includes generating a first virtual layout by placing and routing standard cells using a virtual netlist, searching first duplicate pattern regions in the first virtual layout and choosing one of them as a first representative pattern region, performing an OPC operation on the first representative pattern region to obtain a first OPC result, generating an actual layout by placing and routing standard cells using an actual netlist, performing an OPC operation on the actual layout, and forming a photoresist pattern on a substrate using a photomask manufactured based on the actual layout, to which the OPC operation is applied.

Method of manufacturing a semiconductor device

An integrated circuit (IC) device includes a fin-type active region extending in a first lateral direction on a device region of a substrate. A gate line extends in a second lateral direction on the fin-type active region. The second lateral direction intersects with the first lateral direction. A source/drain region is adjacent to one side of the gate line on the fin-type active region. A gate contact is on the gate line and connected to the gate line. A source/drain contact is on the source/drain region and includes a first segment facing the gate contact and a second segment integrally connected to the first segment. The second segment extends from the first segment in the second lateral direction. In the first lateral direction, a first distance from the first segment to the gate line is greater than a second distance from the second segment to the gate line.

Integrated circuit device

A method of fabricating a semiconductor device is disclosed. The method includes performing an optical proximity correction (OPC) on design patterns of a layout to generate a corrected layout, and forming a photoresist pattern on a substrate using a photomask manufactured based on the corrected layout. The OPC comprises generating develop targets for the design patterns, respectively, choosing first object patterns based on distances between the develop targets, performing a first OPC operation on the design patterns based on a mask rule to generate first correction patterns, choosing second object patterns by considering distances between the first correction patterns and a target error of each of the first correction patterns, and performing a second OPC operation on the first and second object patterns to generate second correction patterns, the performing the second OPC not based on the mask rule.

Optical proximity correction method and method of fabricating a semiconductor device using the same

A non-transitory computer-readable medium storing codes that, when executed by a processor, cause the processor to perform operations of receiving full chip data including specific patterns of a first layout, extracting a representative pattern of the first layout from the full chip data, generating a vector of the extracted representative pattern, generating a first data set based on the generated vector, generating a machine learning model by performing machine learning with respect to the first data set, executing an optical proximity correction (OPC) with respect to the specific patterns of the first layout by using the machine learning model, and generating a second layout based on a result of executing the OPC may be provided.

Method and computing device for manufacturing semiconductor device

Disclosed are mask layout correction methods and a method for fabricating semiconductor devices. The mask layout correction method comprises performing a first optical proximity correction on an initial pattern layout. The step of performing the first optical proximity correction includes providing a target pattern of the initial pattern layout with control points based on a first model, obtaining a predicted contour of the initial pattern layout by performing a simulation, and obtaining an error between the target pattern and the predicted contour from the control points. The control points include first control points on an edge of the target pattern and second control points in an inside of the target pattern. The step of obtaining the error includes acquiring first error values from the first control points, providing weights to the first error values, and acquiring second error values from the second control points.

Mask layout correction method and a method for fabricating semiconductor devices using the same

A method of manufacturing a semiconductor device includes randomly placing a plurality of standard cells from a library in which the standard cells are pre-stored, designing an interconnection pattern in which the standard cells are connected randomly to each other, connecting the standard cells according to the interconnection pattern to generate a virtual layout, performing an optical proximity correction operation on the virtual layout using an optical proximity correction (OPC) model, and forming and verifying a mask corresponding to the virtual layout on which the optical proximity correction operation is performed.

Manufacturing methods of semiconductor devices

A mask fabricating method includes dividing an outline of a first design layout for a target layer into plural segments, selecting interest segments to be biased in a direction of approaching an outline of a second design layout for a lower layer of the target layer, performing optical proximity correction for the target layer based on a first cost function given to each of normal segments and a second cost function given to each of the interest segments, and fabricating the mask corresponding to the first design layout updated based on a result of the optical proximity correction. The second cost function includes a model of a margin between each of the interest segments and the outline of the second design layout. Performing the optical proximity correction includes biasing each of the interest segments up to a boundary defined by the margin.

Method for fabricating mask by performing optical proximity correction

A method for manufacturing a semiconductor device includes obtaining a design layout for a target layer of an optical proximity correction process, the design layout including a first block and a second block being a repetition block of the first block, dividing the design layout into a plurality of patches, performing the optical proximity correction process on the patches of the first block, applying corrected patches of the first block to the patches of the second block, respectively, forming a correction layout by performing the optical proximity correction process on boundary patches of the second block, fabricating a photomask corresponding to the correction layout, and forming patterns on a substrate corresponding to the photomask. Each of the patches is a standard unit on which the optical proximity correction process is performed.

Growing community of inventors

Hwaseong-si, South Korea

Noyoung Chung