Skhynix Inc.

Norton Chu

Fan Zhang

Yu Cai

Chenrong Xiong

Xuanxuan Lu

Jun Feng

Memory controllers and decoders of memory systems and methods for operating the same, which employ smart scheduling of commands to be processed to reduce overall execution time. A metric function is applied to determine or update the priority of each of the multiple commands in multiple queues based on expected execution time and expected wait time such that the smart scheduling scheme provides significant improvement in terms of quality-of-service (QoS) of the memory system.

Controller with smart scheduling and method of operating the controller

A method is provided for operating a storage system including memory cells and a memory controller. Each memory cell is an m-bit multi-level cell (MLC), where m is an integer. The method includes performing a soft read operation of a target memory cell and determining a current LLR (log likelihood ratio) value based on result from the soft read operation. The method also includes grouping m-bit cell values of neighboring memory cells and the target memory cell to respective n-bit indices, based on effect of neighboring memory cells on the LLR of the target memory cell, wherein n is an integer and n&#x3c;m. An LLR compensation value is determined based on the n-bit indices, and a compensated LLR value is determined based on the current LLR value and the LLR compensation value. The method also includes performing soft decoding using the compensated LLR value.

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Norton Chu