International Business Machines Corporation

Globalfoundries U.S. Inc.

Infineon Technologies Ag

Globalfoundries Inc.

Norman Whitelaw Robson

Chandrasekharan Kothandaraman

Dan Moy

John Matthew Safran

Toshiaki Kirihata

Daniel Jacob Fainstein

Arpan Dasgupta

Kirk David Peterson

Darren Lane Anand

Kenneth Jay Stein

Deok-Kee Kim

Yan Zun Li

Keith C Stevens

Mark A DiRocco

Faraz Khan

Danny Moy

Yusheng Bian

Ping-Chuan Wang

Zhong-Xiang He

Douglas Duane Coolbaugh

Subramanian Srikanteswara Iyer

Herbert Lei Ho

Robert Mark Rassel

John Edward Barth, Jr

Sami Rosenblatt

Ebenezer E Eshun

Paul Christian Parries

Hongwen Yan

Gunther Lehmann

Ephrem G Gebreselasie

Yunsheng Song

Troy Lawrence Graves-Abe

Gary William Maier

Teresa Jacqueline Wu

Benjamin Andrew Himmel

Takako Hirokawa

Alberto Cestero

Vaishnavi Karra

Zahidur Chowdhury

John M Safran

Robert Katz

Structures including multiple photonics chips and methods of fabricating a structure including multiple photonics chips. The structure comprises a first chip including a first edge and a first plurality of optical couplers disposed at the first edge, and a second chip including a second edge adjacent to the first edge of the first chip and a second plurality of optical couplers. The second plurality of optical couplers are disposed at the second edge adjacent to the first plurality of optical couplers.

Optical input/output interfaces between photonics chips

Structures including a light source and an edge coupler, and methods of forming and using such structures. The structure comprises a semiconductor substrate and a back-end-of-line stack on the semiconductor substrate. The back-end-of-line stack includes a first dielectric layer, a first plurality of metal features in the first dielectric layer, a second dielectric layer on the first dielectric layer, and a second plurality of metal features in the second dielectric layer. The second plurality of metal features have a non-overlapping relationship with the first plurality of metal features. The structure further comprises an edge coupler adjacent to the first plurality of metal features and the second plurality of metal features.

Photonics chip structures including a light source and an edge coupler

The present disclosure relates to semiconductor structures and, more particularly, to an identification system, method of manufacture and method of use. The structure includes at least one waveguide structure and at least one damaged region positioned in a unique pattern on the at least one waveguide structure.

Identification system

The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.

Charge trap memory devices

The present disclosure generally relates to semiconductor structures and, more particularly, to program and erase memory structures and methods of manufacture. The semiconductor memory includes: a charge trap transistor; and a self-heating circuit which selectively applies voltages to terminals of the charge trap transistor to assist in erase operations of the charge trap transistor.

Program and erase memory structures

According to a method herein, a multi-level inductor is created around a through-silicon-via (TSV) in a semiconductor substrate. A voltage induced in the multi-level inductor by current flowing in the TSV is sensed, using a computerized device. The voltage is compared to a reference voltage, using the computerized device. An electrical signature of the TSV is determined based on the comparing the voltage to the reference voltage, using the computerized device.

Signal monitoring of through-wafer vias using a multi-layer inductor

A method and system for testing one or more semiconductor structures, for example, chips or wafers, in a three-dimensional stack. The method and system includes controlling a logic signal of a first circuit in a first chip or wafer connected to a supply voltage to indicate a first state during pre-assembly testing of the first chip or wafer. The method and system further includes controlling the logic signal to indicate a second state when the first circuit is connected to a second circuit of a second chip or wafer resulting in a combined circuit. The combined circuit is in a three-dimensional chip or wafer stack during post-assembly testing of the three-dimensional chip or wafer stack.

Circuits for self-reconfiguration or intrinsic functional changes of chips before vs. after stacking

One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been relocated due to rotation. A communication channel formed from a pair of pads that are interconnected by a Through Substrate Vias can be placed in each die and can convey selected information from one die to the next. A code representative of the position orientation of each die can be recorded in a Programmable Read Only Memory located on each die, or may be down loaded from a remote source. Any additional wafer may be stacked serially, and each one may be rotated relative to the wafer that precedes it in the stack.

Physical design symmetry and integrated circuits enabling three dimentional (3D) yield optimization for wafer to wafer stacking

A TSV structure, method of making the TSV structure and methods of testing the TSV structure. The structure including: a trench extending from a top surface of a semiconductor substrate to a bottom surface of the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region.

Through-silicon-via with sacrificial dielectric line

A fabrication method for fabricating an electrically programmable fuse method includes depositing a polysilicon layer on a substrate, patterning an anode contact region, a cathode contact region and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, depositing a silicide layer on the polysilicon layer, and forming a plurality of anisometric contacts on the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.

Electrically programmable fuse using anisometric contacts and fabrication method

A random intrinsic chip ID generation employs a retention fail signature. A 1and 2ID are generated using testing settings with a 1setting more restrictive than the 2, creating more fails in the 1ID bit string that includes 2ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1ID includes the 2ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3ID with intermediate condition such that 1ID includes 3ID bit string and 3ID includes 2ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

Retention based intrinsic fingerprint identification featuring a fuzzy algorithm and a dynamic key

An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.

Secure anti-fuse with low voltage programming through localized diffusion heating

An electrically programmable fuse that includes an anode contact region and a cathode contact region are formed of a polysilicon layer having a silicide layer formed thereon, and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, and a plurality of anisometric contacts formed on the silicide layer of the cathode contact region or on both the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.

An antifuse is provided having a unitary monocrystalline semiconductor body including first and second semiconductor regions each having the same first conductivity type, and a third semiconductor region between the first and second semiconductor regions which has a second conductivity type opposite from the first conductivity type. An anode and a cathode can be electrically connected with the first semiconductor region. A conductive region including a metal, a conductive compound of a metal or an alloy of a metal can contact the first semiconductor region and extend between the cathode and the anode. The antifuse can further include a contact electrically connected with the second semiconductor region. In this way, the antifuse can be configured such that the application of a programming voltage between the anode and the cathode heats the first semiconductor region sufficiently to reach a temperature which drives a dopant outwardly therefrom, causing an edge of the first semiconductor region to move closer to an adjacent edge of the second semiconductor region, thus permanently reducing electrical resistance between the first and second semiconductor regions by one or more orders of magnitude.

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Hopewell Junction, NY, United States of America

Norman Whitelaw Robson