Avaya Technology LLC

Lucent Technologies Inc.

At&t Bell Laboratories

American Telephone and Telegraph, Co.

At&t Information Systems Inc.

At+t Corp.

Norman W Petty

Gary L Griffith

Thomas J Tierney, Jr

Chris G Johnson

Douglas A Spencer

Michael L Nienaber

Arthur H Gilmore

Barbara A Seelye

Joel M Ezell

Douglas Anthony Deutsch

Douglas J Rippe

Norman C Chan

Michael A Smith

Isaac K Eyeson

David C Gibbs

Wayne A Zakowski

John S Helton

Ernest J Frey

A low energy detector maintains a sorted list that defines to the circuit removing samples from the queue the location and energy of all samples that fall below the predetermined energy level. This allows a circuit removing samples to execute an algorithm that allows samples to be deleted in accordance with a predetermined pattern.

Apparatus and method to compensate for unsynchronized transmission of synchrous data using a sorted list

Maintaining a count of the number of samples below a predefined energy level that are in the sample queue. This count is then utilized by a circuit that is removing samples from the sample queue to determine which samples to delete in order to maintain a synchronous flow of data to a synchronous physical interface. The samples in the queue are being received from a packet switched network via a voice coder. A low energy detector is utilized to determine the energy level of samples before the samples are placed within the sample queue. This information is then utilized to maintain a counter for the circuit that is removing samples from the sample queue. Utilizing the contents of this counter, the circuit removing samples can determine which samples should be deleted of the ones that have a low energy.

Apparatus and method to compensate for unsynchronized transmission of synchrous data by counting low energy samples

Problems of front-end clipping and excessively long holdover times in digitally encoded speech are resolved by the introduction of a queue at the transmitting end of a digital conversation. Samples are transmitted from the queue until an interval of low energy samples is encountered upon which time samples are not transmitted from queue until energy samples are present.

Apparatus and method for improved voice activity detection

Utilizing an invisible agent within a remote switch to allow the redirection of calls received from a telephone set connected to a public telephone network to a main switching system.

Method and apparatus for automatically directing calls by an invisible agent in a switch

Accurately determining a location of a device by using an acoustic gyroscope within the device The acoustic gyroscope is periodically adjusted using information from external sources.

Apparatus and method for locating devices using an acoustic gyroscope

allowing a central business communication system to handle all aspects of call setup on a remote switch. Call control for a telecommunication call set up on a remote switch continues to be handled by the central business communication system; however, the switching of the bearer channels is performed automatically on the remote switch if the telecommunication call is between telecommunication terminals on the remote switch. In addition, if the telecommunication call is between two remote switches, the remote switches will automatically communicate the bearer channels through an interconnecting media without going through the central business communication system. In addition, when an Internet protocol (IP) such as IETF RFC 791 is utilized to communicate the bearer channels between the central business communication system and the remote switch, multi-frequency dialing tones received from analog telephones connected to the remote switching network are converted to digital information before transmission via the IP communication channels to the central business telecommunication system.

Integration of remote access and service

A computationally-efficient traffic shaper replaces per-virtual-circuit shaping queues that all must be processed during each cell-emission period, with a sequence ( ) of shaping queues ( ) shared by a plurality of virtual circuits and only one of which must be processed during each cell-emission period. N shaping queues are used, where N is the maximum cell delay effected by the traffic shaper divided by the cell emission period; for constant-bit-rate narrowband virtual circuits, N is 47. Each virtual circuit is assigned one or more of the shaping queues, spaced evenly in the sequence, as its serving queues, proportionally to its size. A dequeue state machine ( ) cyclically transmits the contents of a current one of the shaping queues during each period. Per-virtual-circuit instances of an enqueue state machine ( ) each enqueue received ATM cells of its corresponding virtual circuit. If the cell arrives on time, it is enqueued in the current queue which is one of the virtual circuit's serving queues. If the cell arrives early, it is enqueued in the virtual circuit's next serving queue. If the cell arrives late, it is enqueued in the current queue, and designation of all of the virtual circuit's serving queues is shifted an equal amount in the sequence so that the current queue becomes one of the virtual circuit's new serving queues. For variable-bit-rate virtual circuits, an additional overflow queue ( ) is used to temporarily hold overflow received cells until the dequeuing makes room for them in the shaping queues.

Computationally-efficient traffic shaper

A traffic shaper ( ) accommodates F5 maintenance cells of an ATM constant bit rate (CBR) virtual circuit without causing jitter or delay of the CBR traffic cells. Each virtual circuit is allocated two queues: a first queue ( ) for enqueuing CBR traffic cells and a second queue ( ) for enqueuing maintenance cells. Each virtual circuit is allocated twice its normal bandwidth on the transmission medium ( ). A dequeue state machine ( ) transmits contents of each first queue at twice the normal transmission rate during one half of each normal transmission interval of the queue's corresponding virtual circuit, and transmits contents of each second queue at twice the normal transmission rate during the other half of each normal transmission interval of the queue's corresponding virtual circuit. F5 cell transmissions are thus locked half-way between, and 180&deg; out of phase with, transmissions of sequential CBR traffic cells, and consequently introduce no jitter or delay, at the expense of allocated bandwidth.

Traffic shaper that accommodates maintenance cells without causing jitter or delay

A time-slot interchanger (TSI ) is used to control both time-slot access and distribution of signals to physical or virtual signal-processing circuits ( ). The TSI includes a control table ( ) with an entry ( ) for each time slot, that specifies the source ( ) and destination ( ) of signals received during the corresponding time-slot interval and the processing ( ) of those signals. The TSI is coupled to the signal processing circuits, and sends the received signals to the signal processing circuits for processing along with control signals to effect the processing specified by the corresponding control-table entries. For conferencing, the TSI sends all signals for each conference in sequence to the conferencing circuit ( ) before starting and sending any signals for any other conference, thereby allowing a single conference accumulator to support any number of conferences of any size.

Time-slot interchanger that controls both time-slot access and signal-processing features

An ATM cell constructor ( ) of an ATM transmitter assembles a stream of frames of constant bit-rate traffic received on a listen TDM bus ( ) into cell payloads ( ) using ATM adaptation layer (AAL ). Once every eight cells, the AAL structured data transfer (SDT) cell constructor layer ( ) introduces a one-octet SDT offset pointer ( ) into the payload. This pointer designates traffic-block (TDM frame) boundaries. The payload with an attached ATM header forms an ATM cell, and the constructor transmits a stream of the ATM cells to an ATM cell deconstructor ( ) of an ATM receiver. The deconstructor disassembles the payloads of the received ATM cells and transmits the stream of frames of constant bit-rate traffic on a talk TDM bus ( ). In response to each received SDT offset pointer, the deconstructor's time slot interchanger (TSI ) resets to the start of frame-processing, thereby aligning frames formed by the TSI with the received frames. The deconstructor ( ) detects occurrence of TDM frames on the talk TDM bus and synchronizes (aligns) transmission of the frames formed by the TSI with the TDM frames on the talk TDM bus. The listen and talk TDM buses are thereby synchronized with each other.

Arrangement for synchronization of a stream of synchronous traffic delivered by an asynchronous medium

In an asynchronous transfer mode (ATM) disassembler unit that is receiving ATM cells from an optical interface and converting data from these cells onto a constant bit rate (CBR) call, only a nominal predefined build out is defined for each optical interface. If an ATM cell is not received within the proper amount of time for the CBR call from the optical interface, the build out is automatically adjusted so that the build out is equal to the amount of delay that was experienced in receiving the next ATM cell for the call. Only the build out for the individual call that actually experienced the delay of the ATM cell is redefined. The other calls being handled by the optical interface are not effected by this automatic adjustment of the build out interval for the individual call. In addition, when an ATM cell is delayed for a particular call, the information that is transmitted for the call is the last PCM sample of the present ATM cell for that call. This requires in the case of a wideband call that consists of a frame subdivided into a plurality of channels that the frame must be repeated upon an ATM cell being delayed. When the delayed ATM cell is received, all PCM samples for the call are transmitted so that no PCM samples are discarded.

Arrangement for performing automatic build out in a communications system that supports multiple constant-bit-rate connections

An ATM cell constructor (,) limits transmission-delay variations between successive cells of traffic of individual narrowband and wideband channels in a multi-channel environment. Whenever an ATM AAL1 layer (,) of processing completes assembling (,) an ATM cell payload for a narrowband channel (,), it increments (,) a count that anticipates the number of ATM cells that will mature for transmission during the next cell construction period. For wideband channels, a function checks (,) whether traffic from the number of narrowband channels that form the wideband channel will result in completion of assembly of that channel's cell payload during the next cell construction period; if so, the function increments (,) the abovementioned count. The count is reset (,) at the beginning of each cell construction period. Upon receipt (,) of a command to add (start processing) a new channel, a TSI controller (,) compares (,) the count against a threshold that equals the total number of presently-active channels divided by the number of octets of traffic carried by each cell, plus one. If the threshold exceeds the count, the TSI controller sets up (,) a TSI (,) to start processing the new channel; otherwise the TSI controller delays (,) setting up the TSI to process the new channel until occurrence (,) of a cell construction period when the threshold exceeds the count. The net effect is to shift the delay variations from cells of active channels to the start-up of processing of new channels.

Arrangement for minimizing cell-delay variations in a communications system that supports multiple constant-bit-rate connections

An ATM cell constructor (,) of an ATM transmitter assembles a stream of frames of constant bit-rate traffic received on a listen TDM bus (,) into cell payloads (,) using ATM adaptation layer 1 (AAL1). Once every eight cells, the AAL1 structured data transfer (SDT) cell constructor layer (,) introduces a one-octet SDT offset pointer (,) into the payload. This pointer designates traffic-block (TDM frame) boundaries. The payload with an attached ATM header forms an ATM cell, and the constructor transmits a stream of the ATM cells to an ATM cell deconstructor (,) of an ATM receiver. The deconstructor disassembles the payloads of the received ATM cells and transmits the stream of frames of constant bit-rate traffic on a talk TDM bus (,). In response to each received SDT offset pointer, the deconstructor's time slot interchanger (TSI,) resets to the start of frame-processing, thereby aligning frames formed by the TSI with the received frames. The deconstructor (,) detects occurrence of TDM frames on the talk TDM bus and synchronizes (aligns) transmission of the frames formed by the TSI with the TDM frames on the talk TDM bus. The listen and talk TDM buses are thereby synchronized with each other.

Arrangement for synchronization of multiple streams of synchronous traffic delivered by an asynchronous medium

A content-addressable memory (CAM) is implemented by using otherwise-unused memory management unit (MMU 102) and cache memories (104, 105) of a program-controlled microprocessor (100). A program stored in an instruction cache (104) and executed by the microprocessor causes the microprocessor to respond to receipt of a word of data (200), which is illustratively the VPI/VCI of an ATM network connection, by applying the most-significant bits (MSBs 202) of the received word as a comparand to tags (203) of entries (206) of a fully-associative translation buffer (103) of the MMU to obtain an index (204) indicative of which translation buffer entry's corresponding tag matches the comparand. The program further causes the microprocessor to respond to obtaining of the index by concatenating the index with the least-significant bits (LSBs 201) of the received word to form a memory address of a data cache (105) which stores a plurality of records (210) and apply the address to the data cache to retrieve the addressed record, which is illustratively the path of the connection through the ATM network. Entries may be added to and deleted from the translation buffer during processing as needed.

Content-addressable memory implemented with a memory management unit

Port networks (PN 101-103) of a switching system such as a distributed PBX are remoted from and interconnected with each other by an ATM network (100). Each port network includes a port network connectivity (PNC) circuit (113-114) that interfaces it to the ATM network. Only one of the port networks (101) has a system processing element (SPE 111), which controls all of the port networks. Commands issued by the SPE and needed by the ATM network to establish virtual circuits between the port networks are translated (FIG. 2) by a PNC circuit (113) into ATM signaling cells. Commands issued by the SPE and not needed by the ATM network are encapsulated (FIGS. 2 and 3) as payload into ATM traffic cells by the PNC circuit and are sent to destination processor networks through the virtual circuits. At a destination processor network, the encapsulated commands are retrieved (FIGS. 2 and 3) and used for local control. The destination processor networks function as if they were connected directly to the SPE without intermediacy of the ATM network.

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Boulder, CO, United States of America

Norman W Petty