Motorola Corporation

Norman T Rollins

Walter H Kehler

King F Lee

Rajesh H Zele

John Wayne Simmons

Gianfranco Gerosa

Steven P Hoggarth

Virgilio A Fernandez

Man Wa Wong

An auto-adapt circuit ( ) for altering radio receiver parameters due to demodulator transients and preventing the loss of received information. The auto-adapt circuit includes a detector circuit ( ) connected to the output of a receiver demodulator ( ) and a switch ( ) controlled by the detector circuit ( ). The detector circuit ( ) detects a transient voltage at an upper threshold limit or at a lower threshold limit such that a transient at an output of the receiver demodulator will actuate the at least one switch for varying demodulator coupling parameters of the radio receiver.

Automatic adapt circuit for circumventing demodulator transients in radio receiver

A detector circuit (100) for detecting signaling information transmitted with a radio frequency (RF) signal for interpretation by a radio receiver includes a first low pass filter (105) for filtering demodulated audio signals that are directly coupled thereto and for providing a first filtered signal. A second low pass filter (109) is directly coupled with the first low pass filter (105) for filtering the first filtered signal and providing a second filtered signal. A signaling detector (111) is then directly coupled with the second low pass filter (109) for determining the frequency and/or bit code of signaling information included in the second filtered signal.

Direct-coupled signaling receiver with PL/DPL detector

A sampled data filter (400) provides on-chip blocking of DC signals. The addition of a very long time constant (VLTC) integrator (412) into the negative feedback path (414) of a first sampled data integrator (402) provides a lower corner frequency (502) with a zero at DC. The lower corner frequency (502) is adjustable while the desired frequency response is maintained.

DC blocking apparatus and technique for sampled data filters

A volume control circuit comprises a variable gain stage (306), having a variable gain, and an up/down counter (324) for counting. The counter (324) has a counter input (321) and a counter output (333) for providing a first word (333) for controlling the gain of the gain stage. A microprocessor interface (326) includes an interface output (323) for providing a second word. A digital magnitude comparator (333) compares the first (323) and second (333) words. The comparator having a first input (333) connected to the counter output, a second input connected to the interface output (323), and a comparator output connected to the counter input (321), provides a count signal (329) if the words do not match and for providing a non-count signal (329) if the words match. Thus, responsive to the count signal (329), the up/down counter (324), counts from the first word, in a direction approaching the second word by a least significant bit to form a new first word, for controlling the gain of the gain stage.

Volume control device

A method and apparatus for reducing the settling time of a switched-capacitor circuit (10) which includes at least one capacitor (20) having at least one terminal connected to a switch. The method comprises the step of clocking the switched-capacitor circuit at a switching clocking frequency. In response to a control signal (51), the at least one terminal of the at least one capacitor (20) is biased to a reference voltage potential.

Switched-capacitor circuit power down technique

A circuit (100) is provided which includes a forward charging switch (FET MN2) having an input terminal (102), an output terminal 112 and a plurality of current sink elements (FETs MN1 and MN3). The plurality of current sink elements (MN1 and MN3) are selectable via a control switch circuit (114) which is responsive to a control signal at the control switch input terminal (104). Preferably, one of the current sinks is always selected in order for some small amount of current to be discharged from output terminal 112 which is coupled to a capacitor (C1).

Circuit with adjustable release time

A master-slave flip-flop having a first bistable cell and a control circuit coupled to that first cell for changing the binary state of the cell in response to a set of complementary data inputs and a clock signal. The slave portion of the flip-flop includes a second bistable cell that is coupled to the first cell and a second control circuit for changing the state of the second cell in response to the output of the first cell and to a clock signal. The flip-flop is intended to be implemented using CMOS technology, and is capable of performing at frequencies greater than a gigahertz with low power consumption. The circuit configuration is highly symmetric, so that the master and slave portions may be interchanged.

Growing community of inventors

Sunrise, FL, United States of America

Norman T Rollins