Qualcomm Incorporated

Norman S Gargash

Brian J Salsbery

Vinod Vijayarajan

Andrew James Frantz

Bohuslav Rychlik

Sumit Sur

Steven S Thomson

Ali Iranli

Tracy A Ulmer

Rodney Wayne Smith

Raguram Damodaran

Ryan Donovan Wells

Jeffrey Todd Bridges

Shivam Priyadarshi

Anil Krishna

Joshua Stubbs

Praveen Kumar Chidambaram

Gabriel A Watkins

Yizheng Zhou

Grady L Caraway

Sean Sweeney

Christopher A Barrett

Robert Nicholson Gibson

Mark D Guzzi

Purandar Mukundan

Michael Abel

Chris Barrett

Andrew J Frantz

Joshua H Stubbs

Sean D Sweeney

The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.

Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase

The aspects enable a computing device or microprocessor to determine a low power mode that provides the most system power savings by placing selected resources in a low power mode while continuing to function reliably, depending upon the resources not in use, acceptable system latencies, dynamic operating conditions (e.g., temperature), expected idle time, and the unique electrical characteristics of the particular device. Aspects provide a mechanism for determining an optimal low power configuration made up of a set of low power modes for the various resources within the computing device by determining which low power modes are valid at the time the processor enters an idle state, ranking the valid low power modes by expected power savings given the current device conditions, determining which valid low power mode provides the greatest power savings while meeting the latency requirements, and selecting a particular low power mode for each resource to enter.

Dynamic low power mode implementation for computing devices

The aspects enable a computing device or microprocessor to determine a low-power mode that maximizes system power savings by placing selected resources in a low power mode while continuing to function reliably, depending upon the resources not in use, acceptable system latencies, dynamic operating conditions (e.g., temperature), expected idle time, and the unique electrical characteristics of the particular device. The various aspects provide mechanisms and methods for compiling a plurality of low power resource modes to generate one or more synthetic low power resources from which can be selected an optimal low-power mode configuration made up of a set of selected synthetic low power resources.

Domain specific language, compiler and JIT for dynamic power management

Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees for a group of processors to ensure that the processors does not remain in a busy state (e.g., due to transient workloads) for a combined period that is more than a predetermined amount of time above that which is required for one of the processors to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of one or more of the processors based on a variable delay to ensure that the multiprocessor system only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processors.

System and method for controlling central processing unit power with guaranteed transient deadlines

In a portable computing device having a node-based resource architecture, resource requests are batched or otherwise transactionized to help minimize inter-processing entity messaging or other messaging or provide other benefits. In a resource graph defining the architecture, each node or resource of the graph represents an encapsulation of functionality of one or more resources controlled by a processor or other processing entity, each edge represents a client request, and adjacent nodes of the graph represent resource dependencies. A single transaction of resource requests may be provided against two or more of the resources. Additionally, this single transaction may become forked so that parallel processing among a client issuing the single transaction and the resources handling the requests of the single transaction may occur.

Batching and forking resource requests in a portable computing device

A method of dynamically controlling power within a central processing unit is disclosed and may include entering an idle state, reviewing a previous busy cycle immediately prior to the idle state, and based on the previous busy cycle determining a CPU frequency for a next busy cycle.

System and method for controlling central processing unit power with reduced frequency oscillations

Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees to ensure that a processor does not remain in a busy state (e.g., due to transient workloads) for more than a predetermined amount of time above that which is required for that processor to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of a processor based on a variable delay to ensure that the processing core only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processor.

Resource state sets corresponding to the application states are maintained in memory. A request may be issued for a processor operating in a first application state corresponding to the first resource state set to transition to a second application state corresponding to the second resource state set. A start time to begin transitioning resources to states indicated in the second resource state set is scheduled based upon an estimated amount of processing time to complete transitioning. A process is begun by which the states of resources are switched from states indicated by the first resource state set to states indicated by the second resource state set. Scheduling the process to begin at a time that allows the process to be completed just in time for the resource states to be immediately available to the processor upon entering the second application state helps minimize adverse effects of resource latency.

System for minimizing resource latency between processor application states in a portable computing device by scheduling resource state set transitions

A method and system for managing resources of a portable computing device is disclosed. The method includes receiving node structure data for forming a node, in which the node structure data includes a unique name assigned to each resource of the node. A node has at least one resource and it may have multiple resources. Each resource may be a hardware or software element. The system includes a framework manger which handles the communications between existing nodes within a node architecture. The framework manager also logs activity of each resource by using its unique name. The framework manager may send this logged activity to an output device, such as a printer or a display screen. The method and system may help reduce or eliminate a need for customized APIs when a new hardware or software element (or both) are added to a portable computing device.

System and method for managing resources and threshsold events of a multicore portable computing device

A method of executing a dynamic clock and voltage scaling (DCVS) algorithm in a central processing unit (CPU) is disclosed and may include monitoring CPU activity and determining whether a workload is designated as a special workload when the workload is added to the CPU activity.

User activity response dynamic frequency scaling processor power management system and method

Requests of a PCD are determined if they are part of a transaction involving a plurality of resources. Next, each resource that is part of the request involving multiple resources is identified. As each resource is identified, a framework manager determines if a resource has completed processing the request directed at it. If the resource has returned a value that it has completed the request, then the framework manager allows the resource to return to an unlocked state while other requests in the transaction are being processed. If the resource has not completed processing and has deferred some of the processing to the end of the transaction, then the resource is added to a deferred unlock list. It is determined if the resource is a dependent on another resource in the current request path. If it is dependent, then the other resource is also placed on the deferred unlock list.

Tracking and releasing resources placed on a deferred unlock list at the end of a transaction

A method of controlling power at a central processing unit is disclosed. The method may include moving to a higher CPU frequency after a transient performance deadline has expired, entering an idle state, and resetting the transient performance deadline based on an effective transient budget.

The aspects enable a multi-core processor or system on chip to determine a low power configuration that provides the most system power savings by placing selected resources in a low power mode depending upon acceptable system latencies, dynamic operating conditions (e.g., temperature), expected idle time, and the unique electrical characteristics of the particular device. Each of the cores/processing units treated in a symmetric fashion, and each core may choose its operating state independent of the other cores, without performing complex handshaking or signaling operations.

Dynamic sleep for multicore computing devices

In a portable computing device having a node-based resource architecture, resource requests are batched or otherwise transactionized to help minimize inter-processing entity messaging or other messaging or provide other benefits. In a resource graph defining the architecture, each node or resource of the graph represents an encapsulation of functionality of one or more resources controlled by a processor or other processing entity, each edge represents a client request, and adjacent nodes of the graph represent resource dependencies. A single transaction of resource requests may be provided against two or more of the resources.

Growing community of inventors

Boulder, CO, United States of America

Norman S Gargash