Texas Instruments Corporation

Other

North American Philips Corporation

Norman L Culp

William Robert Krenik

Eugene G Dierschke

Hugh Thomas Mair

Xiaoyu Xi

Franco Maloberti

Keith Edmund Kunz

Franck Benjamin Dahan

Stephen C Kwan

Siew Kuok Hoon

Jun Chen

William G Miller

Kenneth G Buss

Sudha Thiruvengadam

James Sangwon Song

Steven C Brummette

William Douglas Wilson

Donald Thomas Pullen

James F Asbury

Chih-Hung Lin

A battery charger and system and method for use of the same are disclosed for increasing a charge of a battery. In one embodiment of the battery charger, an input for an electric charging power source is configured to supply electrical charging power to a rechargeable battery via an output circuit portion interposed therebetween. A transfer function circuit portion is configured to sense the voltage of the rechargeable battery as a sensing voltage such that the change in the sensing voltage is directly proportional to the internal impedance of the rechargeable battery. A control logic circuit portion is configured to select between a constant current, variable voltage operational mode, a constant current, scalable voltage operational mode, and a variable current, constant voltage operational mode to furnish rapid recharging of the rechargeable battery.

Battery charger and system method

A battery charger system and method are disclosed for increasing a charge of a battery. In one embodiment of the battery charger, an input for an electric charging power source is configured to supply electrical charging power to a rechargeable battery via an output circuit portion interposed therebetween. A transfer function circuit portion is configured to sense the voltage of the rechargeable battery as a sensing voltage such that the change in the sensing voltage is directly proportional to the internal impedance of the rechargeable battery. A control logic circuit portion is configured to select between: a constant current, variable voltage operational mode; a constant current, scalable voltage operational mode; and a variable current, constant voltage operational mode to furnish rapid recharging of the rechargeable battery.

Battery charger system and method

One embodiment of the present invention includes a system for managing power of a memory array. The system comprises a comparator configured to compare a first voltage with a reference voltage. The first voltage can correspond to an operating voltage of at least one of a peripheral circuit associated with the memory array and a logic circuit configured to communicate with the peripheral circuit. The reference voltage can correspond to a minimum threshold voltage for read/write operations of the memory array. The system also comprises an output circuit configured to provide an output voltage to the memory array in response to an output of the comparator. The output voltage can be the greater of the operating voltage of the at least one of the peripheral circuit and the logic circuit and the minimum threshold voltage.

Systems and methods for managing power

A switching regulation system and control scheme efficiently enables driving multiple loads from a common energy storage element, such as an inductor. The control scheme operates to store energy in the energy storage element over a first portion of a cycle, such as by ramping up current through an inductor, according to energy requirements of the multiple loads. After storing the energy in the storage element during the first portion of the cycle, the stored energy is delivered consecutively to each of the multiple loads over a subsequent portion of the cycle.

DC/DC power converter

A output driver architecture ( ) is proposed that uses thin gate-oxide core and thin gate-oxide Drain-extended transistors that can directly interface with voltage supplies up to six times the normal rating of the transistor. A bias generator ( ), level shifter ( ) and output stage ( ) are adapted to buffer an input signal with a voltage swing of less than the normal operating voltage of the transistors to an output signal with a voltage swing of up to approximately six times the normal operating voltage of the transistors. The bias generator is interfaced directly with a high voltage power supply and generates a bias voltage with a magnitude of less than the dielectric breakdown of the transistors internal to the level shifter and output stage. Further, the bias generator is adapted to sense the magnitude of the high voltage supply, and to automatically and continuously self-adjust the bias voltage in response to changes sensed in the magnitude of the high voltage supply such that the bias generator can be used for a continuous range of high voltage supplies up to 6 times the normal operating voltage of the transistors.

Versatile high voltage outputs using low voltage transistors

An integrated circuit resistor (18) has a layout in which a first parasitic capacitance (26) exists between first portions of the resistor (18) and a first integrated circuit feature (34), and a second parasitic capacitance (28) exists between second portions of the resistor and a second integrated circuit feature (32). The resistor (18) may have, for example, a zigzag or serpentine configuration, with portions of each leg of the zigzag configuration overlying the first and second integrated circuit features (34,32). The first and second integrated circuit features (34,32) are configured to produce substantially canceling charges on the first and second parasitic capacitances (26,28). The resistor may be defined by a doped semiconductor material, such as a polysilicon layer. The resistor may be used in many applications, such as a feedback resistor of an optoelectronic current-to-voltage converter (12).

Charge cancellation technique for integrated circuit resistors

An integrated circuit resistor (18) has a layout in which a first parasitic capacitance (26) exists between first portions of the resistor (18) and a first integrated circuit feature (34), and a second parasitic capacitance (28) exists between second portions of the resistor and a second integrated circuit feature (32). The resistor (18) may have, for example, a zigzag or serpentine configuration, with portions of each leg of the zigzag configuration over-lying the first and second integrated circuit features (34,32). The first and second integrated circuit features (34,32) are configured to produce substantially canceling charges on the first and second parasitic capacitances (26,28). The resistor may be defined by a doped semiconductor material, such as a polysilicon layer. The resistor may be used in many applications, such as a feedback resistor of an optoelectronic current-to-voltage converter (12).

A clamp circuit including a clamping capacitor and a differential amplifier charge and discharge the clamping capacitor in accordance with the magnitude of difference signals applied to the differential amplifier's inverting and non-inverting inputs. The inverting input receives the voltage produced by the clamping capacitor. This voltage is digitized by an analog-to-digital converter (ADC) and is set to a reference voltage range by a voltage divider network. The ADC output signal is compared to a given reference level corresponding to a selected voltage in the reference voltage range to produce a difference output signal. This difference output signal is summed with the selected voltage in the reference voltage range and applied to the non-inverting input of the differential amplifier to produce a clamp voltage with substantially minimum offsets due to the amplifier, ADC and DAC. A clamp enable signal operates the clamping circuit during a blanking interval of a video signal applied to the clamping capacitor. A digital processing circuit of a television receiver receives the video signal clamped to the level of the clamp voltage. Instead of processing the video signal at the clamped level, a blanking signal code word is inserted in the clamped video signal to save memory. The video signal applied to the digital processing circuit is thus clamped to the voltage level by the inserted code word.

Clamping circuit with offset compensation for analog-to-digital

A method and apparatus for an improved multiple channel sensor interface circuit is described which comprises a plurality of input integrator circuits (35) coupled in parallel; a switched capacitor multiplexer (37) coupled to the input integrator circuits (35); and an output integrator stage (39) coupled to the switched capacitor multiplexer (37). An additional embodiment is described wherein a multiple channel voltage sensor interface circuit comprising a plurality of switched capacitor storage elements (S26 . . . S28) is coupled to a plurality of inputs; a plurality of integrator amplifiers (51, 53) is coupled to the switched capacitor storage elements (C22 . . . C30); and timing circuitry is coupled to the switched capacitor storage elements (C221 . . . C30) and to integrator amplifiers (51, 53) operable to selectively enable sampling of the inputs.

Method and apparatus for an improved multiple channel sensor interface

A transient protection circuit comprising using a circuit connected to operate as a diode while presenting lower forward voltage drop for the same area and current as in pn junction diodes to provide greater efficiency. The circuit is a standard merged SCR circuit wherein a resistive path is provide between the base and collector of the pnp transistor and between the base and emitter of the npn transistor. In addition, there is provided a trip circuit wherein current is shunted away from the lateral transistor after a predetermined threshold current is passed through said transistor to minimize current drawn through the later transistor.

Transient protector

An annunciator is disclosed which has an improved charging circuit for storing the energy of a ring signal received via an improved Schottky diode bridge rectifier, and an oscillator-driven variable divider which actuates an audible output device when the stored charge exceeds a threshold level.

Growing community of inventors

Montgomery, TX, United States of America

Norman L Culp