International Business Machines Corporation

Apple Inc.

Norman Jay Rohrer

Kerry Bernstein

Paul David Kartschoke

Vinod Ramadurai

Christopher J Gonzalez

Victor Zyuban

Keith Alan Cox

Edward J Nowak

Philip George Emma

John Atkinson Fifield

William A Klaasen

Kirk David Peterson

Cedric Lichtenau

Stephen Victor Kosonocky

Michael John Hargrove

Fariborz Assaderaghi

John Gregory Dorsey

Yizhang Yang

Peter Edwin Cottrell

Peter I Smeys

Liang Deng

Arpit Mittal

Jeffrey P Gambino

Jack Allan Mandelman

Steven H Voldman

John J Ellis-Monaghan

Alain F Loiseau

Randy William Mann

Peter Anthony Sandon

Gilles Gervais

Antonietta Oliva

Alberto Garcia Ortiz

David A Cain

Jeffrey W Sleight

Christopher David Muzzy

Leland Chang

Shreesh Narasimha

Frank David Ferraiolo

Robert H Dennard

Kevin John Nowka

Shawn Searles

Stephen Edward Greco

Nazmul Habib

Erik L Hedberg

John E Gersbach

James A Culp

Douglas Willard Stout

David Meltzer

Cyril De La Cropte De Chanterac

Ronald Dennis Rose

Charles Joseph Masenas

Paul Stephen McLaughlin

Leendert M Huisman

Barry Watson Krumm

James S Ismail

Eric Adler

Leah M P Pastel

Jeffrey Scott Zimmerman

Daryl Michael Seitzer

Sribalan Santhanam

Jody John Van Horn

Jean E Wynne

Jeffery Howard Oppold

Mark R Bilak

Ashish R Jain

Jenifer E Lary

Allen Prescott Haar

Thomas G Mitchell

Zachary E Berndlmaier

Jennifer E Appleyard

Ching Elizabeth Ho

Dae-Young Jung

Christopher W Chaney

Bruce W Singer

Timothy Jon Sulzbach

Sung Wook Kang

Dean G Percy

Nimish Kabe

Neela Lohith Penmetsa

Joseph M Forbes

Alberto Garcia-Ortiz

Daryl M Seltzer

Troy Carlson

Mohamed H Abu-Rama

William J Tanona

In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate.

Dynamic refresh rate control

A converter circuit, included in a power converter circuit, may generate a given voltage level on a regulated power supply node of a computer system. A control circuit may monitor a voltage level and assert a control signal in response to a determination that a regulation event has occurred. A boost converter circuit, included in the power converter circuit, may inject charge into to the regulated power supply node via a capacitor, in response to an assertion of the control signal.

Power converter with charge injection from booster rail

In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

Method for multiplexing between power supply signals for voltage limited circuits

Embodiments provide for a computer implemented method comprising sampling one or more power and performance metrics of a processor; determining an energy cost per instruction based on the one or more power and performance metrics; determining an efficiency metric based on the energy cost per instruction; computing an efficiency control error based on a difference between a current efficiency metric and a target efficiency metric; setting an efficiency control effort based on the efficiency control error; determining a performance control effort, the performance control effort determined by a performance controller for the processor; and adjusting the performance control effort based on the efficiency control effort, wherein adjusting the performance control effort reduces power consumption of the processor.

Processor unit efficiency control

Techniques are disclosed relating to dual-edge triggered (DET) clock gater circuitry. In some embodiments, an apparatus includes a first series of DET clock gater circuits configured, when the DET clock gater circuits are not gating an input clock signal, to provide an output clock signal to sequential circuitry. In some embodiments, ones of the DET clock gater circuits are controlled by respective control signals and are configured to maintain a mode indicator indicating whether or not the DET clock gater circuit is inverting the polarity of its input clock when generating an output clock. In some embodiments, the apparatus also includes a first adjustable delay circuit configured to adjust delay imposed on the output clock signal from the first series of DET clock gater circuits based on the number of DET clock gater circuits in the series that are in a particular mode.

Balancing delay associated with dual-edge trigger clock gaters

In an embodiment, a lifetime controller is configured to monitor operating conditions for a device, and to control operating conditions based on the previous conditions to improve the reliability characteristics of the device while permitting strenuous use as available. For example, the lifetime controller may permit strenuous use when the device is first powered on. Once a specified amount of strenuous use has occurred, the controller may cause the operating conditions to be reduced to reduce the wear on the device, and thus help to extend the lifetime of the device. Similarly, if a device is used in less strenuous conditions, the controller may accumulate credit which may be expended by permitting the device to operate in more strenuous conditions for a period of time.

Controlling electrical device based on temperature and voltage

Embodiments relate to modulating a power supply voltage for varying a propagation delay of data paths within an integrated circuit. The power supply voltage is modulated to increase the delay of shorter data paths for reducing an incidence of hold time violations without substantially affecting the delay of longer data paths. For example, the power supply voltage is reduced from a nominal value in the first half clock cycle to increase delay of both the shorter data paths and the longer data paths. The power supply voltage is increased from the nominal value in the second half clock cycle to decrease delay of the longer data paths within the second half clock cycle such that the overall delay of the longer data paths is virtually same as when the power supply voltage is fixed at the nominal value for the entire clock cycle.

Modulation of power supply voltage for varying propagation delay

In an embodiment, the amount of supply voltage guardband to prevent incorrect operation due to aging effects may be modeled using an IC-specific age model generated early in the product life cycle of the IC. For example, high temperature operating life (HTOL) testing may be performed at multiple temperatures and/or voltages to develop the IC-specific age model. The IC-specific age model may be more accurate then the calculations used to develop guardband voltage as discussed previously, which rely on the aging of a single transistor. The IC-specific age model may be used along with monitoring of the aging effects during operation of the IC to predict an amount of increased guardband voltage that is currently desirable to apply to the IC. The predicted amount may vary from about zero when the IC is new to the full amount of guardband voltage when the IC is nearing end of life.

Reliability guardband compensation

A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.

Optimizing voltage on a power plane using a host control unit to control a networked voltage regulation module array

Growing community of inventors

Underhill, VT, United States of America

Norman Jay Rohrer