Hughes Aircraft Company

Etag Systems, Inc.

Norman E Moyer

Ernest C Ho

Richard J Belardi

John N Whipple

Irving B Merles

Methods for efficiently querying and identifying multiple items on a communication channel are disclosed. The methods preferably use radio frequency identification with interrogation devices and systems that identify radio frequency identification transponders. A depth-first tree traversal protocol algorithm, including commands and symbols, preferably is used to more efficiently interrogate a plurality of transponders in a short amount of time. The communication channel may be an RFID communication channel or a wired communication channel. The time required to obtain the identification numbers of the objects may be made deterministic. The objects to be identified may be clothing, luggage, furniture, computers, parcels, vehicles, warehouse inventory, components on an assembly line or documents.

Deterministic Method for efficiently querying and identifying multiple items on a communication channel

Deterministic method for efficiently querying and identifying multiple items on a communication channel

Systems and methods for efficiently querying and identifying multiple items on a communication channel are disclosed. The inventions preferably uses radio frequency identification with interrogation devices and systems that identify radio frequency identification transponders. A depth-first tree traversal protocol algorithm, including commands and symbols, is used to more efficiently interrogate a plurality of transponders in a short amount of time.

Method for efficiently querying and identifying multiple items on a communication channel

A method for identifying objects using an interrogation device on a communication channel is disclosed. Each object has an identification number in the form of a plurality of digits and has the ability to communicate to the interrogating device at least two different predetermined responses to indicate the value of the digits contained in its identification number. The objects are activated, and a single digit from currently activated objects is interrogated, and each object sends one of the predetermined responses. The value of the received responses is recorded, and those objects which responded with any but one of the at least two different messages are signaled to enter a deactivated state when two of the at least two different messages are received. The sequence of responses transmitted and received thus far for those objects placed in the deactivated state are recorded. Objects will no longer respond until the step of activating is repeated. The steps are selectively repeated until all of the predetermined responses are obtained for the complete identification number of at least one of the objects. The steps may thereafter be selectively repeated until the identification number of each of the objects is obtained.

In the NOVRAM cell of the present invention, a pair of cross-coupled variable threshold floating gate MOS (VTMOS) transistors facilitates nonvolatile and non-inverting writing and reading of data in the memory cell. The disadvantages of the prior art are overcome by completely disconnecting the VTVMOS transistors from the remainder of the memory cell during normal volatile writing and reading operations. Accordingly, during normal writing and reading operations the NOVRAM cell of the present invention performs just as if the pair of cross-coupled VTVMOS transistors were not even present, so that there is no problem of leakage currents or instability due to excessive charging or discharging of the floating gates of the VTVMOS transistors.

Nonvolatile random access memory cell

An electrically erasable programmable read-only memory, comprising a plurality of floating gate tunneling metal oxide semiconductor field effect transistors, does not require an addressing transistor in each cell. Instead, the gate decoder applies a sufficiently negative gate voltage to unselected ones of the transistors so that they are turned off regardless of the amount of charge on their floating polysilicon gates. Writing and erasure of data is performed without disturbing data in memory cells not selected for writing or erasure despite the absence of a series connected addressing transistor.

Electrically erasable programmable read-only memory cell having a single

In a CMOS FATMOS EEPROM, in which a floating gate and its associated tunneling region overlies the source to drain channel, device density is dramatically improved by sharing a source diffusion between adjacent FATMOS transistors and by reversing the function of the source and drain diffusions between reading and writing operations. During writing of a logic 'one' into an individual memory cell, the shared diffusion and the control gate are held at +18 volts while the well region is grounded and the other diffusion is selectively grounded.

Electrically erasable programmable read-only memory cell having a shared

A light emitting diode (LED) digital watch with circuitry which allows the watch user to adjust the amount of time the horological information is displayed and to adjust the brightness of the display.

LED Digital watch with user control of display timing and brightness

In a digital watch, frequency adjusting can be achieved by selectively deleting pulses at a specified location in the divider chain in order to obtain the desired timekeeping accuracy. When a digital watch's recessed (setting) push button is sequentially depressed, the watch's display advances through the month, date, hours and minutes/seconds setting modes. If the recessed push button is depressed again, the watch will be in the coarse frequency adjust mode and the letters 'CFA' are shown on the watch display for approximately one second, the display is blanked for 0.5 second, and then the watch shows a three digit frequency correction number with the first two digits flashing. By holding down a main operating push button, the flashing number increments at a one Hertz rate until the desired coarse frequency correction number is shown on the watch display. An additional push of the recessed push button puts the watch in the fine frequency adjust mode and the letters 'FFA' are shown on the watch display for approximately one second, the display is blanked approximately 0.5 seconds, and the same three digit frequency correction number appears with the last digit flashing. By holding down the main push button, the flashing digit is incremented at a one Hertz rate until the desired fine frequency correction number is obtained at which time the main push button is released.

Digitally tuned timepiece

A logic circuit subsection of a digital watch integrated circuit (IC) chip which enables the final watch electronics module to determine whether it is in a two or three button watch. The IC chip then uses this information to alter the pushbutton responses so that it is appropriate for either a two or three button watch. The logic circuit of the present invention consists of a plurality of logic gates in combination with latching means which cause the digital watch to be in either a two or three button mode. In the two button digital watch, by placing the batteries in the watch the circuit of the present invention causes the watch to be in the two button mode, and to thereby function as a two button watch. Simultaneous depression of both of the watch's buttons will also cause the watch to be in the two button mode. In the three button watch, depression of the third button will cause the watch to be in the three button mode and to thereby function as a three button watch.

Logic circuit for use in two or three button digital watch

An analog output circuit for a digital correlator that may be completely integrated with the digital correlator on a single CMOS/LSI chip. The output circuit includes a compensating arrangement so that its output voltage is substantially unaffected by internal processing variables between different chips or by external variables such as temperature or supply voltages. The circuit includes a reference MOS unit and a correlation MOS unit each including parallel arranged PMOS transistors respectively coupled in series with first and second NMOS transistors. An operational amplifier biased to a voltage V.sub.REF is coupled between the reference MOS unit and the gates of the first and second NMOS transistors. The circuit operates to bias the gate of the second NMOS transistor so that constant output voltage steps are provided in the series path between the correlation MOS unit and the second NMOS transistor as long as variations of operating parameters track each other uniformly between the PMOS units and between the NMOS transistors.

Output circuit for a digital correlator

A digital LED display watch is provided with 1) an operating button to select and control display of data in the normal operating mode, and 2) a recessed button to select separately for possible setting each unit of horological data except seconds. The display of the data selected for possible setting is flashed, and the actual advancing is controlled by the operating button. The data displayed in the normal mode is timed hours-minutes, separated by a colon, with seconds after hours-minutes if the operating button is held down, and month-date separated by a dash if the operating button is pushed twice. In the setting mode, data not being set (but otherwise associated in the display with data that is) is blanked, but the colon or dash is retained. During setting of hours the dash is added to the colon during the first 12 hours of each day to indicate AM. An optional recessed button is provided to manually select the duty cycle of the LED display and thus alter apparent brightness and power consumed.

Digital watch with two buttons and improved setting and display control

A digital timing circuit in a digital watch with a two digit display. When said circuit is activated by a push button, the two display elements first display the hours information, next are blank for a short duration, then display the minutes information, then go blank until the button is pushed again.

Timing circuit for display sequencing in a digital wristwatch

A timing circuit in a digital watch with a two digit display. When the circuit is activated by a push button, the two display elements first display the hours information, for as long as the push button is depressed, and after release of the push button, the display elements show minutes for about one-half second before turning off.

Growing community of inventors

Newport Beach, CA, United States of America

Norman E Moyer