Gte Laboratories Incorporated

Norman E Heckman

Christopher W Kapral

Jagannath P Agrawal

A concurrent echo cancellation and channel equalization signal processor for hybrid full duplex communication, including a decision device and three transversal adaptive filters, in which the gain coefficients of the three transversal filters are adjusted in accordance with a fast Kalman algorithm to minimize the error between the estimated far end signal after it has passed through a hybrid (produced by summing the filter outputs) and the estimated received far end signal (produced by the decision device).

Adaptive echo cancellation and equalization system signal processor and

A system includes arithmetic logic units, each including two 2:1 multiplexers, one 8:1 multiplexer, and a three input majority gate. Each 2:1 multiplexer provides a specific one of two data inputs when a select input signal is at a specific one of two binary states. The 8:1 multiplexer provides output signals indicative of specific ones of eight data inputs in accordance with the binary states of three select input signals. Electrical signals indicative of two input variables are coupled, respectively, to the select input of the two 2:1 multiplexers. Two outputs therefrom are coupled to two of three select inputs of the 8:1 multiplexer, and to two inputs of the majority gate. A carry-in signal is coupled to both the third select input of the 8:1 multiplexer, and to the third input of the majority gate. The arithmetic logic unit acts as an adder, subtractor, AND gate, OR circuit, exclusive OR circuit, and NOR circuit. Arithmetic and logical functions on two input binary variables of the form A.sub.0, A.sub.1. . .A.sub.n and B.sub.0, B.sub.1. . .B.sub.n are performed by an arithmetic logic system comprising n+1 arithmetic logic units. The output of the majority gate of one logic unit is coupled to the carry-in signal receiving means for following logic unit. With appropriate control signals, the system acts as an adder by providing a sum function at the respective outputs of the 8:1 multiplexer, and provides a carry-out function at the output of the (n+1)st logic unit majority gate.

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Concord, MA, United States of America

Norman E Heckman