National Semiconductor Corporation

Norman E Abt

Reza Moazzami

Yoav Nissan-Cohen

David Wingto Cheung

Sheldon Aronowitz

Michael P Brassington

William H Shepherd

James M Jaffe

Shi-Qing Wang

Peter A McNally

Anne K Gregory

An electrical ceramic oxide capacitor utilizable in an integrated circuit memory device, and a method for making same is presented. A transistor is fabricated on a semiconductor substrate according to conventional techniques. A diffusion barrier is deposited over the transistor to protect it from subsequent process steps. Metal contacts are formed to contact the active transistor regions in the substrate, and additional barriers are formed to insulate the metal contacts. In a vertical embodiment, the barriers above the metal contacts can serve as bottom electrodes for the capacitor. In a lateral embodiment, the barriers on the side of the metal contacts serve as electrodes for the capacitor. Electrical ceramic oxide material is deposited between the electrode plates.

High density electrical ceramic oxide capacitor

Method for forming a ceramic oxide capacitor having barrier layers

A multi-step plasma etch method for etching a tapered via having uniform bottom diameter ('CD') and extending through the resist and into the oxide layer of a coated semiconductor substrate, and a coated semiconductor substrate whose coating has been plasma etched to define such a tapered via. The first step of the inventive method is an anisotropic oxide plasma etch operation, preferably employing a plasma consisting primarily of CF.sub.4, which produces a non-tapered via having diameter substantially equal to CD and extending through the resist and into the oxide layer. A preferred embodiment of the inventive method includes a second step defining an upper sloping via portion without significantly increasing the diameter of a lower portion of the non-tapered via. This second step is a tapered resist plasma etch operation employing a mixture of oxygen (O.sub.2) and CF.sub.4. The slope of the upper sloping via portion may be controlled by varying the ratio of oxygen to CF.sub.4. In an alternative embodiment, the method produces a 'stepped' via having an upper non-tapered portion which extends through the resist and has an opening diameter substantially greater than CD, and a lower non-tapered portion which extends through the oxide and has diameter substantially equal to CD.

Method for plasma etching tapered and stepped vias

A screening process for ferroelectric memory devices that provides a greater degree of confidence in the mechanical and thermal stability of the ferroelectric material than prior art screening processes. A correspondingly higher degree of confidence in the reliability of the screened part results.

Screening processes for ferroelectric memory devices

Materials of the lead perovskite family PbZr.sub.x Ti.sub.1-x O.sub.3 have been discovered to be excellent masking materials in the etching of silicon and silicon-containing materials with chlorine and fluorine -based plasmas. Generally, materials of the lead perovskite family are suitable masking materials for any material that is etched in chlorine and fluorine -based plasmas.

Masking material for applications in plasma etching

The present invention provides a process for patterning ruthenium. A layer of ruthenium is formed on a substrate. The ruthenium is masked. The ruthenium is exposed to an oxygen plasma.

Method for plasma etch of ruthenium

A ferroelectric random access memory device contains columns of ferroelectric memory cells, each column of memory cells being coupled to a distinct bit line. Each memory cell is selectively coupled to a corresponding bit line by an access control transistor so that only one memory cell in the column is coupled to the bit line at a time. To read the data stored in a selected memory cell reads, the cell is strobed twice, separately sampling the output voltage generated each time. Since the first read is a destructive read, the second read operation always reads the cell in its '0' state. Then the two sampled outputs are compared, and if the first reading exceeds the second by at least a threshold amount then a '1' output value is generated. Otherwise a '0' is the output value. In a preferred embodiment, the time delay between strobing the memory cell and sampling its output is made longer the first time that the cell is read than for the second time that the cell is read. In this way, if the cell is storing a '0' bit, the first read will produce an output voltage that is smaller than it would have been had the first read not been delayed, which helps to ensure that cells storing '0' bit values are properly sensed.

Growing community of inventors

Burlingame, CA, United States of America

Norman E Abt