International Business Machines Corporation

Norman C Chou

Moon Jung Kim

Michael Steven Siegel

Leslie W Wyman

Albert James Van Norstrand, Jr

Casper A Scalzi

Roger E Hough

Peter H Gum

James Charles Gregerson

Donald W McCauley

James R Robinson

Edward J D'Avignon

James C Mazurowski

John Fenton Scanlon

Michael A Smoolca

A method and system for enhancing processing efficiency in a data processing system which includes multiple scalar instruction processors and a vector instruction processor. An ordered sequence of intermixed scalar and vector instructions is processed in a nonsequential order by coupling those instructions to selected processors. As each instruction is finished an indication of that state is stored within a finish instruction array. The first vector instruction within the ordered sequence is initiated within the vector instruction processor only after an indication that each scalar instruction preceding the first vector instruction is finished. A vector advance signal is generated by the vector instruction processor each time processing of a vector instruction is initiated. A subsequent vector instruction is then initiated when the vector processor assets are available only in response to the presence of the vector advance signal and an indication that all scalar instructions which proceed the subsequent vector instruction within the ordered sequence have finished, without encountering an exception. In this manner, chained processing of vector instructions may be accomplished by initiating processing of a subsequent vector instruction only after possible interruption by a scalar instruction exception is no longer possible.

Method and system for nonsequential execution of intermixed scalar and

A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions.

CPU expansive gradation of I/O interruption subclass recognition

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Poughkeepsie, NY, United States of America

Norman C Chou