Fujitsu Corporation

Noriyuki Tokuhiro

Hiroshi Miyazaki

Yasutaka Kanayama

Michitaka Hashimoto

Hiroshi Miyake

Kunihiro Itoh

Ryo Mizutani

Tadao Aikawa

Masazumi Maeda

Kazumasa Kubotera

Shinya Aiso

Noriyuki Takahashi

Tatsuya Sakae

Katsuhiko Ookubo

A PAM reception circuit includes a first comparison circuit that outputs a first bit value in two-bit values based on a result of a comparison between a reception signal of pulse amplitude modulation 4 in which the two-bit values are associated with four potential levels divided by three threshold values by gray codes and a first threshold value which is a center of the three threshold values, an absolute value circuit that outputs an absolute value of a difference between the reception signal and the first threshold value or a negative value obtained by inverting a sign of the absolute value from a positive sign to a negative sign, and a second comparison circuit that outputs a second bit value in the two-bit values based on a result of a comparison between a second threshold value which is larger than the first threshold value in the three threshold values.

PAM reception circuit and reception apparatus

A delay circuit includes: a delay line that delays an input signal in accordance with a delay setting signal and performs output of the input signal as a delayed signal; and a logic circuit processes the input signal to the delay line and the delayed signal.

Test method of delay circuit including delay line

A receiving circuit that receives differential data strobe signals between a controller and a memory, the receiving circuit includes: a first receiver that compares one of the differential data strobe signals to the other, output a high logic value when the one of the differential data strobe signals is higher than the other, and output a low logic value when the one is lower than the other; a second receiver that compares one of the differential data strobe signals to a strobe reference voltage, output a high logic value when the one of the differential data strobe signals is higher than the strobe reference voltage, and output a low logic value when the one of the differential data strobe signals is lower than the strobe reference voltage; and a determination circuit that outputs a logical OR of an output of the first receiver and an output of the second receiver.

Receiving circuit, memory interface circuit, and receiving method

An EVEN component selecting unit and an ODD component selecting unit acquire a first signal from a DQ signal based on a rising edge of a DQS signal and a second signal from the DQ signal based on a falling edge of the DQS signal. Variable delay adding units give the first signal a first delay based on a phase difference between an internal clock signal and the rising edge of the DQS signal and give the second signal a second delay based on a phase difference between the internal clock signal and the falling edge of the DQS signal. Data capturing units capture, based on the internal clock signal, data from the first signal to which the first delay is given and the second signal to which the second delay is given.

Signal control circuit, information processing apparatus, and signal control method

A memory controller has a first variable delay circuit that delays a data strobe signal received from a memory, and a second variable delay circuit that variably delays a data signal which is received from the memory and is synchronous with the data strobe signal, and that is set a second delay amount which is different from a first delay amount of the first variable delay circuit.

Memory controller and information processing device

A signal control circuit includes: a delay acquisition circuit configured to obtain a first delay amount to be added to an input signal for aligning timing of rise of the input signal with timing of fall or rise of a reference signal and a second delay amount to be added to the input signal for aligning timing of fall of the input signal with timing of the fall or the rise of the reference signal; and a ratio calculation circuit configured to calculate a duty ratio of the input signal based on a difference between the first delay amount and the second delay amount.

Signal control circuit, information processing apparatus, and duty ratio calculation method

A semiconductor apparatus includes a phase detecting unit that continuously detects a first delay amount during a read operation, based on a phase difference between an external clock signal and an internal clock signal; a generating unit that generates a second control signal by delaying a first control signal by a second delay amount that when added to the first delay amount, the sum is a specific time period, a valid time period of the first control signal starts when the read operation starts and is at least to equal a read time for one data signal and less than the specific time period that is from the start of the read operation until output of a received data signal; and a delay control unit that delays the data signal by the first delay amount detected at a start of a valid time period of the generated second control signal.

Semiconductor apparatus

A PMOS output stage and an NMOS output stage of which output impedances are controlled in accordance with impedance codes, a gate control part which drives output transistors held by the PMOS output stage and the NMOS output stage, and a slew rate control part which generates bias voltages to control driving ability of the gate control part based on an input current are included, and manufacturing variability of an input current circuit generating an input current is corrected by using the impedance code by the slew rate control part.

Driver circuit and semiconductor device

A signal restoration circuit includes a storage configured to store input signals by disposing the input signals in an input order, the input signals being readable from the storage in the disposed order, and a storage controller configured to control delay time from an input of the input signal to an output in the storage based on delay information of the input signal.

Signal restoration circuit, latency adjustment circuit, memory controller, processor, computer, signal restoration method, and latency adjustment method

A level converter includes a level conversion circuit, which is provided between a reference power supply line having a reference voltage level and a first power supply line coupled to a first power supply outputting a first voltage level, which inputs a first signal and outputs a second signal, the first signal having a first logic level and a second logic level, the second signal having a first logic level and a second logic level; a control signal generating circuit to output a control signal having the reference voltage level when a second power supply outputting the second voltage level is turned off and the first voltage level when the second power supply is turned on; and a coupling circuit to control an electrically connection between the first power supply line and an output node of the level conversion circuit based on the control signal.

Level converter and processor

A signal receiving circuit includes a phase detection unit and a delay control unit. The phase detection unit detects a phase difference between a received signal and a clock signal. The delay control unit receives the phase difference, delays a phase of the received signal in a range not exceeding a delay amount determined by using a predetermined phase difference as a unit, and changes, when the phase difference exceeds the predetermined phase difference, a delay amount of the received signal by using the predetermined phase difference as a unit.

Signal receiving circuit, memory controller, processor, computer, and phase control method

In a semiconductor device, a selector selects a different reference voltage depending on whether the impedance of a transmitter or of a receiver is to be adjusted, and causes a reference voltage generator to generate the selected reference voltage. The reference voltage generator generates the reference voltage selected by the selector and applies the generated reference voltage to an impedance adjuster. The impedance adjuster adjusts the impedance of the transmitter and the impedance of the receiver, separately from each other, in accordance with the input reference voltage.

Semiconductor device, circuit board device, and information processing device

A memory control circuit has a write leveling function and controls read/write operations by supplying a clock signal to a plurality of memories through a clock signal line which is wired to the plurality of memories through daisy chain connection. For each of the plurality of memories, a first variable delay unit delays, in a write operation, a data strobe signal output to the memory by a first delay time that is set by utilizing the write leveling function and a second variable delay unit delays, in a read operation, a data signal input from the memory by a second delay time that is set based on the first delay time.

Delay time control of memory controller

A driver circuit for driving a device or circuit disposed after it comprises a plurality of driving transistors connected in parallel, a selection unit for selecting one or more groups from a plurality of groups to each of which driving transistors having a power base of two with the same polarity belong and in which the number of driving transistors belonging to each group is different and a driving unit for driving driving transistors belonging to the group selected by the selection unit.

Driver circuit

A digital DLL device is provided which can reduce an error with respect to a target delay amount. The device provides a delay to an input clock signal so as to equally divide a clock cycle T thereof into N parts, and includes first variable delay sections and second variable delay sections, each of which is formed of an arbitrary number of unit delay buffers connected in series with one another. A phase comparison section makes a compare between the phase of the input clock signal and the phase of an output signal which is the input signal having been delayed while passing through all the first and second variable delay sections, and outputs a result of the comparison. A delay control section calculates a total number of unit delay buffers S required based on the phase comparison result, sets a quotient Q of S divided by N to be the number of unit delay buffers for each of the first variable delay sections, and allocates a remainder R of S divided by N to the second variable delay sections, respectively.

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Kawasaki, Japan

Noriyuki Tokuhiro