Fujitsu Corporation

Noriyuki Takahashi

Noriyuki Tokuhiro

Mikio Hondou

Shinya Aiso

A signal restoration circuit includes a storage configured to store input signals by disposing the input signals in an input order, the input signals being readable from the storage in the disposed order, and a storage controller configured to control delay time from an input of the input signal to an output in the storage based on delay information of the input signal.

Signal restoration circuit, latency adjustment circuit, memory controller, processor, computer, signal restoration method, and latency adjustment method

A priority control registerdynamically controls the internal transition state based on the issuability state of a memory request obtained in the memory request issuability signal generation unitand retaining state of the memory request in the REQ_BUFobtained by each of determination circuitsthrough #. Thus, the jump control of the priorities corresponding to the access regulation of the DRAM modulecan be realized.

Growing community of inventors

Kawasaki, Japan

Noriyuki Takahashi