Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Noriyuki Nagai

Koji Takemura

Atsushi Doi

Tomoyuki Nakayama

Manabu Ohnishi

Hoyeun Huh

Masao Takahashi

Naoki Nojiri

Kiyomi Hagihara

Shigefumi Dohi

Toshihiko Sakashita

Takatoshi Osumi

A semiconductor device includes: a first semiconductor chip; a second semiconductor chip placed such that a front face of the second semiconductor chip faces a front face of the first semiconductor chip, and being smaller in size than the first semiconductor chip; an expansion portion extending outward from at least one side face of the second semiconductor chip; a wiring board placed such that a front face of the wiring board faces the front face of the first semiconductor chip and a back face of the second semiconductor chip; and a first interconnect formed on the back face of the second semiconductor chip and a back face of the expansion portion, and being in connection to the wiring board.

Semiconductor device

A semiconductor device includes a semiconductor substrate, an interlayer insulating filmformed on the semiconductor substrate, an electrode padformed on the interlayer insulating film, a protective filmwhich is formed on the interlayer insulating filmto cover a peripheral portion of the electrode pad, and has a first openingwhich exposes a center portion of the electrode pad, a dividerwhich is formed on the electrode padexposed from the first opening, and divides the first openinginto a plurality of second openings, and a barrier metalformed on the protective filmto fill the second openings. The divideris interposed between the electrode padand the barrier metal

Protection film having a plurality of openings above an electrode pad

Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.

Semiconductor device having a pad-disposition restriction area

A semiconductor device includes: a semiconductor element () having an internal circuit (); and electrode pads (, . . . ) provided for the semiconductor element (). The electrode pads (, . . . ) are electrically connected to the internal circuit () via control portions () for controlling electrical connection between the electrode pads (, . . . ) and the internal circuit ().

Semiconductor device and fabrication method for the same

The bump electrodeof the present invention has a structure in which dummy metalsare provided in the uppermost layer portion of a siliconbetween a pad-form wiring metaland a wiring metalsuch that an edge of each dummy metal and an edge of the barrier metalare not aligned in a line, and a lot of interfaces are formed between the dummy metalsand an interlayer film, and therefore expansion of a crack generated due to bump stress concentrated on the under-edge portionbelow the barrier metalbetween the pad-form wiring metaland the wiring metalis suppressed.

Electrode structure for semiconductor chip with crack suppressing dummy metal patterns

A semiconductor device in which a chipis mounted on a board, includes: a pad group A provided on the chipand electrically connected to an internal circuit in the chip; and a test pad pattern B provided on a region of the chipexcept for a region of the chipwhere the pad group A is provided. The pad group A includes: padsformed on a principal surface of the chip; bumpsrespectively formed on the padswith a barrier metal layer interposed therebetween, and electrically connected to the board. The test pad pattern B includes: test padsformed on the principal surface of the chip; test bumpsrespectively formed on the test padswith a test barrier metal layer interposed therebetween, and interconnectselectrically connecting adjacent ones of the test pads

Semiconductor device including chip

When manufacturing a semiconductor device by mounting a semiconductor chipon a substratewith a flip-chip method, projectionsare formed between padsarranged in multiple annular concentric layers on the semiconductor chipother than padsarranged along the innermost periphery thereof. On the substrate, bonding resinis dispensed onto an area inside the innermost periphery along which the padsare arranged. By heating and applying pressure, the bonding resinis spread over the entire gap between the substrateand the semiconductor chipso as to secure the substrateto the semiconductor chipby the bonding resin, thereby preventing a void from being formed in an area outside the innermost periphery along which the padsare arranged and thus stabilizing an electrical connection state between the semiconductor chipand the substrate

Semiconductor device and method of manufacturing the same

In a semiconductor device, a pad metal has at least a portion located immediately under a probe region, and the portion is divided into a plurality of narrow metal layers each arranged in parallel with a traveling direction of a probe. Thus, it is possible to enhance surface flatness of the pad metal and to prevent a characteristic of a semiconductor device from deteriorating without complication in processing and increase in chip size.

Semiconductor device having a probing region

According to the invention, in input/output circuit portions positioned around a semiconductor chip, electrode pads are arranged above each of a plurality of input/output cells arranged in a line. The width of the electrode pads is greater than the width of the input/output cells, and thus the electrode pads cannot be arranged in a single line and are instead arranged staggered in two lines. The electrode pads of one row are arranged shifted so that they do not overlap with the internal terminals of the input/output cells, but are disposed near these internal terminals. The spacing between the electrode pads is set to a distance that is at least a set distance determined by the isolation rules of the design.

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Nara, Japan

Noriyuki Nagai