Adv Antest Corporation

Mercene Labs Ab

Noriyuki Masuda

Masatoshi Sato

Shinichi Hashimoto

Kiyoto Nakamura

Katsumi Ochiai

Tommy Haraldsson

Hidenobu Matsumura

Kazuo Takano

Carl Fredrik Carlborg

Masayuki Suzuki

Henrik Mikaelsson

Seiji Hideno

A method for making three dimensional structures using photolithography and an adhesively bondable material is disclosed. A thiol-ene-epoxy (OSTE(&#x2212;)) material undergoes a first reaction upon partial irradiation in a pattern to become a partially cross-linked polymer network. Non-cross-linked parts are dissolved in a solvent and removed. An initiator is added to activate the cross-linked polymer network so that it becomes adhesive and can then be covalently bound to another object to form an article. The method can be utilized to manufacture an article with a complicated three dimensional shape in an easy way.

Method for making three dimensional structures using photolithography and an adhesively bondable material

A test carrier includes a base member on which a first electronic device under test is able to be temporarily mounted, and a second electronic device which is configured to be used to test the first electronic device. The second electronic device is mounted on the base member, and the second electronic device is able to be electrically connected to the first electronic device.

Test carrier for mounting and testing an electronic device

A test carrier includes a base member that holds a die and a cover member. The base member includes a board having a wiring line that is electrically connected to the die. The wiring line includes a wiring line and a resistive portion having a resistance value that is higher than the resistance value of the wiring line.

Test carrier

A measurement apparatus comprising a serial resistor in series with an element under measurement; a switching section that sequentially selects ends of a serial circuit including the element under measurement and the serial resistor, and ends of the serial resistor; an applying section that applies an application voltage or application current corresponding to a preset setting value, to each of the sequentially selected ends; a measuring section that, for each of the sequentially selected ends, measures current when the applying section applies the application voltage corresponding to the setting value and measures voltage when the applying section applies the application current corresponding to the setting value; and a resistance calculating section that calculates the resistance value of the element under measurement, based on either the setting values set sequentially in the applying section or measured values measured sequentially by the measuring section for each of the sequentially selected ends.

Measuring apparatus and measuring method

A semiconductor test system is capable of generating timing edges in the same direction having a time interval smaller than a reference clock cycle. The semiconductor test system includes a waveform memory for storing edge data which defines edges of a test signal waveform, a timing generator for generating timing data and a timing pulse for each test cycle, a wave formatter for generating a set signal and a reset signal for producing the test signal waveform in response to the timing data and the timing pulse, and a virtual timing generator for detecting a relationship between previous edge data and current edge data from the waveform memory and removing the current edge data when the current edge data is the same as the previous edge data and allocating the current edge data to a time position where there is an actual change of edge in the test signal waveform.

Semiconductor test system

A timing edge forming circuit includes a pattern generator for generating address data, a rate signal and pattern data, a first logic delay circuit for generating first delay time data by the address data wherein the first delay time data includes a first multiple delay time which is an integer multiple of one cycle of the clock signal and a first fractional delay time which is smaller than one cycle of the clock signal, and for sending an enable signal in synchronism with the clock signal which is delayed by the first multiple delay time and the first fractional delay time, a logic delay control circuit for adding the first fractional delay time to skew data to form second delay time data, a second logic delay circuit for providing a second multiple delay time in the second delay time data which is an integer multiple of one cycle of the clock signal to the enable signal, and for producing a second fractional delay time which is smaller than one cycle of the clock signal, a variable delay circuits for providing a high resolution delay time to the delayed enable signal based on the second fractional delay time.

Timing edge forming circuit for IC test system

Pattern data comprising N=8 words, where one word comprises m=3 bits, delivered in parallel from a pattern memory 2 is input to a parallel/serial conversion circuit 3. The circuit 3 can be switched between a serial output mode (MC='0') in which data for one word per pin is serially delivered every test cycle and a parallel-serial output mode in which parallel data for n-2 words per pin (m.times.n bits) are serially delivered every test cycle in response to a mode control signal MC.

Test pattern generator circuit for IC testing equipment

Timing generating circuit and method

Temperature compensation circuit for IC chip

A timing generator for generating delay timing signals which have delay time up to n-times of a reference clock period is capable of considerably reducing the hardware size. The timing generator is used in a semiconductor testing apparatus. The timing generator can contribute to reduce the total size and cost of the semiconductor testing apparatus. The timing generator includes a counter for counting the reference clock, an adder for adding the output of the counter to delay data, a series of registers for storing the output of the adder and shifting the output of the adder in synchronism with a delay trigger signal, a series of exclusive OR gates for comparing each output of the registers with the output of the counter and generating coincidence signals when the output from the register and the counter coincide with each other, and an OR gate for receiving the outputs of the exclusive OR gates and generating a signal which is combined of the outputs from the exclusive OR gates.

Growing community of inventors

Tokyo, Japan

Noriyuki Masuda