Nec Electronics Corporation

Noriyuki Kodama

Koichi Sawahata

Morihisa Hirata

Hitoshi Irino

In a semiconductor device, a well region is formed in a semiconductor substrate, a transistor-formation region is defined in the well region. An electrostatic discharge protection device is produced in the transistor-formation region, and features a multi-finger structure including a plurality of fingers. A guard-ring is formed in the well region so as to surround the transistor-formation region, and a well blocking region is formed in the well region between the transistor-formation area and the guard-ring. A substrate resistance determination system is associated with the electrostatic discharge protection device to determine a substrate resistance distribution at the transistor-formation area such that snapbacks occur in all the fingers in a chain-reaction manner, and such that occurrence of a latch-up state is suppressed.

MOS type semiconductor device having electrostatic discharge protection arrangement

An electro-static discharge protection device includes a first conductive type well and a second conductive type well which are formed in a surface of the first conductive type layer or a first conductive type substrate. A first high concentration second conductive type region, a first high concentration first conductive type region, and a second high concentration second conductive type region are formed in a surface of the second conductive type well. A third high concentration second conductive type region is formed in a surface of the first conductive type well. The first high concentration second conductive type region and the first high concentration first conductive type region are connected with a first power supply of a potential. The third high concentration second conductive type region is connected with a second power supply having a potential different from the potential of the first power supply. The second high concentration second conductive type region is set to a potential different from the first power supply.

Electro-static discharge protection device

In a semiconductor device having an electrostatic discharge protection arrangement, a semiconductor substrate exhibits a first conductivity type. First and second impurity regions each exhibiting a second conductivity type are formed in the semiconductor substrate. A channel region is formed in the semiconductor substrate between the first and second impurity regions. A first conductive area is defined on the first impurity region in the vicinity of the channel region. A second conductive area is defined on the first impurity region so as to be supplied with an electrostatic discharge current. A third conductive area is defined on the first impurity region to establish an electrical connection between the first and second conductive area. At least one heat-radiation area is defined in the third conductive area so as to be at least partially isolated therefrom and thermally contacted with the first conductive area.

There is provided an electrostatic discharge protection device comprising a P conductive type first P well regionformed in a P type epitaxial layerbeing deposited on a surface of a P+ substratehaving a prescribed thickness, an N conductive type first N wella periphery thereof being brought into direct contact with and surrounded by a first P well region, P conductive type first P diffusion regionsand, a P conductive type third P diffusion region, and an N conductive type second N diffusion regionarranged within a first P well region, and a P conductive type second P diffusion regionand an N conductive type first N diffusion regionarranged within a first N well

Electrostatic discharge protection device

A multifinger ESD protection element has between an input wiring to which a surge current is input and a reference-potential wiring, 2n-number (where n is a natural number of 2 or greater) of fingers Fto F. A drain resistor Rd(i=1 to 2n), NMOS transistor Tand source resistor Rsare connected serially in each finger Fin the order mentioned. A single unit Uis constructed by two mutually adjacent fingers Fand F(where j is a natural number of 1 to n). In each unit the source of one transistor is connected to the gate of the other transistor and the source of this other transistor is connected to the gate of the first-mentioned transistor. The source Sof finger Fis connected to the source Sof the next unit U. The 2n-number of fingers are connected in the form of a ring.

Multifinger-type electrostatic discharge protection element

An N well is formed in a surface of a P substrate and a P well is formed in such a way as to surround the N well. Then, a trigger tap (P diffusion region) is formed in the surface of the P well and two cathodes (N diffusion regions) are formed in such a way as to hold the trigger tap. Then, an anode (P diffusion region) is formed in the surface of the N well in a position facing the trigger tap and the cathode, and an N well pick-up diffusion (N diffusion region) is formed in such a way as to surround that side edge of the anode which does not face the cathode. Accordingly, the resistance between the end portion of the anode and the N well pick-up diffusion (N diffusion region) becomes lower than the resistance between the center portion of the anode and the N well pick-up diffusion.

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Kanagawa, Japan

Noriyuki Kodama