Fuji Electric Co., Ltd.

National Institute of Advanced Industrial Science and Technology

Fuji Electric Device Technology Co., Ltd.

Fuji Electric Systems Co. Ltd.

Fuji Electric Holdings Co., Ltd.

National Institute of Advanced Industrial Science

Noriyuki Iwamuro

Yuichi Harada

Shinsuke Harada

Yasuyuki Hoshi

Tadayoshi Iwaana

Kenji Fukuda

Akimasa Kinoshita

Takashi Tsuji

Manabu Takei

Haruo Nakazawa

Koh Yoshikawa

Akio Sugi

Kouta Takahashi

Atsushi Tanaka

Masahide Goto

In an embodiment, on an ntype SiC layer on an n-type SiC semiconductor substrate and a player selectively formed on the ntype SiC layer, a p base layer is formed on which, a pcontact layer is selectively formed. From a surface, an n counter layer penetrates the p base layer to the ntype SiC layer. A gate electrode layer is disposed via a gate insulating film, on an exposed surface of the p base layer between the pcontact layer and the n counter layer; and a source electrode contacts the pcontact layer and the p base layer. In a back surface, a drain electrode is disposed. A portion of the players are joined at a region of a drain electrode side of the n counter layer, by a joining unit and a player contacts a drain electrode side of the player.

High voltage semiconductor device

A silicon carbide vertical MOSFET includes an N-counter layer of a first conductivity type formed in a surface layer other than a second semiconductor layer base layer selectively formed in a low concentration layer on a surface of the substrate, a gate electrode layer formed through a gate insulating film in at least a portion of an exposed portion of a surface of a third semiconductor layer of a second conductivity type between a source region of the first conductivity type and the N-counter layer of the first conductivity type, and a source electrode in contact commonly with surfaces of the source region and the third semiconductor layer. Portions of the second conductivity type semiconductor layer are connected with each other in a region beneath the N-counter layer.

Vertical high voltage semiconductor apparatus and fabrication method of vertical high voltage semiconductor apparatus

A p-type region, a ptype region, and a ptype region are selectively disposed in a surface layer of a silicon carbide substrate base. The p-type region and the ptype region are disposed in a breakdown voltage structure portion that surrounds an active region. The ptype region is disposed in the active region to make up a JBS structure. The ptype region surrounds the p-type region to make up a junction termination structure. A Schottky electrode forms a Schottky junction with an n-type silicon carbide epitaxial layer. The Schottky electrode overhangs an interlayer insulation film covering a portion of the p-type region and this overhanging portion acts as a field plate. The ptype region has an acceptor concentration greater than or equal to a predetermined concentration and can make a forward surge current larger.

Silicon carbide semiconductor device and fabrication method of silicon carbide semiconductor device

A Ptype region, a p-type region, and a Ptype region are disposed in a surface layer of a silicon carbide substrate base and are disposed in a breakdown voltage structure portion surrounding an active region to make up an element structure of Schottky junction. The ptype region surrounds the Ptype region and the p-type region to form a junction termination structure. A Schottky electrode forms a Schottky junction with an n-type silicon carbide epitaxial layer. The Schottky electrode and an electrode pad have end portions positioned on the Ptype region and the end portion of the Schottky electrode is exposed from the end portion of the electrode pad. As a result, the region of the breakdown voltage structure portion can be made smaller while the active region can be made larger, and a semiconductor device is easily fabricated.

A silicon carbide semiconductor device has a first-conductivity-type semiconductor layer having a lower impurity concentration and formed on a first-conductivity-type semiconductor substrate, a second-conductivity-type semiconductor layer having a higher impurity concentration and selectively formed in the first-conductivity-type semiconductor layer, a second-conductivity-type base layer having a lower impurity concentration formed on a surface of the second-conductivity-type semiconductor layer, a first-conductivity-type source region selectively formed in a surface layer of the base layer, a first-conductivity-type well region formed to penetrate the base layer from a surface to the first-conductivity-type semiconductor layer, and a gate electrode formed via a gate insulation film on a surface of the base layer interposed between the source region and the well region. Portions of the respective second-conductivity-type semiconductor layers of different cells can be connected to each other by a connecting portion in a region under the well region.

Silicon carbide semiconductor device and fabrication method thereof

In an active region, pregions are selectively disposed in a surface layer of an ndrift layer on an nsemiconductor substrate. A p-base layer is disposed on surfaces of the ndrift layer and the Pregions, and an MOS structure is disposed on the p-base layer. In another portion of the active region, a pregion is disposed to be in contact with the source electrode on the pregions. In a breakdown voltage structure region (), a JTE structure having at least a Pregion is disposed separately from the Pregions and the p-base layer, to surround the active region. The Pregion is electrically in contact with the Pregion in a portion in which the MOS structure is not formed, in the vicinity of the boundary between the active region and the breakdown voltage structure region.

Semiconductor device

A base layer is used that has an N-type SiC layer formed in a surface layer on the front surface side of an N-type SiC substrate, and a P-type region is formed on a surface of the N-type SiC layer with an N-type source region selectively formed in a surface layer of the P-type region. A source electrode is formed on a surface of the N-type source region and a drain electrode is formed on the back surface side of the N-type SiC substrate. Additionally, the gate electrode is formed via a gate insulation film only on a surface of the P-type region. In this way, high electric field is no longer applied to the gate insulation film on the surface of the N-type SiC layer due to stoppage of voltage application to the gate electrode.

Semiconductor device with SiC base layer

A wide bandgap semiconductor device includes a first conductive type high-concentration wide bandgap semiconductor substrate, a first conductive type low-concentration wide bandgap semiconductor deposited film which is formed on the semiconductor substrate, a metal film which is formed on the semiconductor deposited film so that a Schottoky interface region is formed between the metal film and the semiconductor deposited film, and a second conductive type region which is formed in a region of the semiconductor deposited film corresponding to a peripheral portion of the metal film, wherein the Schottoky interface region in the semiconductor deposited film is surrounded by the second conductive type region so that periodic island regions are formed in the Schottoky interface region.

Wide bandgap semiconductor device

A vertical high voltage semiconductor apparatus includes a first conductivity semiconductor substrate; a first conductivity semiconductor layer disposed on the semiconductor substrate and having an impurity concentration lower than the semiconductor substrate; a second conductivity semiconductor layer disposed on the first conductivity semiconductor layer; a second conductivity base layer disposed on the first conductivity semiconductor layer and the second conductivity semiconductor layer and, having an impurity concentration lower than the second conductivity semiconductor layer; and a first conductivity source region selectively disposed inside the base layer. In an edge termination portion, after a region of the second conductivity semiconductor layer is removed, in the first conductivity semiconductor layer having an impurity concentration lower than that of the semiconductor substrate, second conductivity layers having a low concentration are formed such that the second conductivity layer at the innermost perimeter, the second conductivity semiconductor layer, and the base layer do not contact.

High voltage semiconductor apparatus

To provide a vertical SIC-MOSFET and IGBT capable of having low ON-resistance without destruction of gate oxide films or degradation of reliability even when a high voltage is applied, and a fabrication method thereof, a vertical mosfet has a semiconductor layer and a base layer joined instead of a well regionso as to include, as a joining portion, a point that is farthest and equidistant from centers of all the source regions facing each other and that is closest and equidistant from end portions farthest from the centers of the source regions in a planar view.

Vertical high-voltage semiconductor device and fabrication method thereof

An n-type SiC layer is formed on a front face of an n-type SiC substrate and plural p-type regions are selectively formed inside the n-type SiC layer. A p-type SiC layer is formed covering the surfaces of the n-type SiC layer and the p-type regions. An n-type region is formed inside the p-type SiC layer to be connected to the n-type SiC layer. An n-type source region and a p-type contact region are formed inside the p-type SiC layer, positioned away from the n-type region and in contact with each other. The n-type region in the p-type SiC layer is formed such that the width Lof the n-type region is within a range from 0.8 &#x3bc;m to 3.0 &#x3bc;m and the impurity concentration of the n-type region is greater than 1.0&#xd7;10cmand less than or equal to 5.0&#xd7;10cm.

A wide band gap semiconductor device is disclosed. A first trench in a gate electrode part and second trench in a source electrode part (Schottky diode) are disposed close to each other, and the second trench is deeper than the first trench. A metal electrode is formed in the second trench to form a Schottky junction on a surface of an n-type drift layer in the bottom of the second trench. Further, a p+-type region is provided in part of the built-in Schottky diode part being in contact with the surface of the n-type drift layer, preferably in the bottom of the second trench. The result is a small wide band gap semiconductor device which is low in on-resistance and loss. Electric field concentration applied on a gate insulating film is relaxed to suppress lowering of withstand voltage and increase avalanche breakdown tolerance at turning-off time.

Wide band gap semiconductor device and method for producing the same

A silicon carbide vertical field effect transistor includes a first-conductive-type silicon carbide substrate; a low-concentration first-conductive-type silicon carbide layer formed on a surface of the first-conductive-type silicon carbide substrate; second-conductive-type regions selectively formed on a surface of the first-conductive-type silicon carbide layer; first-conductive-type source regions formed in the second-conductive-type regions; a high-concentration second-conductive-type region formed between the first-conductive-type source regions in the second-conductive-type region; a source electrode electrically connected to the high-concentration second-conductive-type region and a first-conductive-type source region; a gate insulating film formed from the first-conductive-type source regions formed in adjacent second-conductive-type regions, onto the second-conductive-type regions and the first-conductive-type silicon carbide layer; a gate electrode formed on the gate insulating film; and a drain electrode on the back side of the first-conductive-type silicon carbide substrate, wherein an avalanche generating unit is disposed between the second-conductive-type region and the first-conductive-type silicon carbide layer.

Silicon carbide vertical field effect transistor

A first metal layer () is formed on a back face of a silicon carbide substrate () to a degree such that the first metal layer () does not fully cover the back face of the silicon carbide substrate. Many holes () are formed on the back face of the silicon carbide substrate () by dry-etching the back face of the silicon carbide substrate () using the first metal layer () as a mask therefor. A second metal layer constituting an ohmic contact is formed on the first metal layer () and the back face of the silicon carbide substrate () including inner surfaces of the many holes ().

Growing community of inventors

Tsukuba, Japan

Noriyuki Iwamuro