Hitachi, Ltd.

International Business Machines Corporation

Fujitsu Corporation

Nec Corporation

Rikagaku Kenkyusho

Hitachi Device Eng.

Noriyuki Honma

Kunihiko Yamaguchi

Goro Kitsukawa

Takao Watanabe

Ryoichi Hori

Kazuo Kanetani

Hiroaki Nanbu

Kiyoo Itoh

Masahiro Iwamura

Masaharu Kubo

Ikuro Masuda

Isao Yoshida

Tohru Nakamura

Hiroaki Nambu

Hisayuki Higuchi

Tetsuya Hayashida

Makoto Suzuki

Kazuhiko Sagara

Eiichi Goto

Kazuo Nakazato

Kiyoo Ito

Motoaki Matsumoto

Kenichi Ohata

Kazuhiko Tani

Motoaki Matumoto

A dynamic random access memory device is provided having a dynamic memory cell, a word line coupled to the dynamic memory cell, a data line coupled to the dynamic memory cell, a precharge circuit coupled to the data line, a word driver coupled to the word line and a decoder coupled to the word driver. A plurality of address lines coupled to the decoder. The decoder has a first logic circuit whose inputs are connected to the plurality of address lines. The decoder also has a latch circuit whose input is connected to an output of the first logic circuit and whose output is connected to the word line.

Dynamic random access memory having bipolar and C-MOS transistor

A clock signal distributing system supplies clock signals exhibiting extremely matched phases as a standing wave without employing extra signals such as a reference signal and the like other than clock signal itself. The system compensates for a phase lag in clock signal sand attenuation in signal amplitude. As a result, clock signals exhibiting extremely matched phases are supplied up to the places to be distributed at the respective terminals without requiring equal-length wiring on, for example, a semiconductor chip. The clock signal distributing system is composed of an electromagnetic transmission path line which transmits periodic clock signals as a standing wave, an amplifier, and a phase advancing unit which advances phases of the periodic clock signals wherein a phase lag in transmission of clock signals and a phase lag in amplitude of the amplifier are corrected in the phase advancing direction by the phase advancing unit.

Clock signal distributing system

A dynamic random access memory is provided which includes word lines for accessing memory cells, data lines for transferring information from the memory cells, and rewrite amplifiers connected to the data lines for rewriting the information to corresponding memory cells. Read pre-amplifiers are also provided for sensing the information, together with common data lines for transferring output signals of the read pre-amplifiers. Each of the read pre-amplifiers has two insulated gate field-effect transistors, gates of which are connected to the data lines, and sources/drains of which are connected with the common data lines, such that the common data lines do not form current paths with the data lines. In addition, the read pre-amplifiers are activated before the rewrite amplifiers.

Dynamic random access memory including read preamplifiers activated

A bipolar memory of a construction having high immunity from soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuit of the memory cell, are inverted, and the load device thereof has a shielding arrangement for shielding the flip flop from the noise produced within the substrate. Either pnp type transistors or Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in the region where the device is provided. A reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.

Radiation resistant bipolar memory

Herein disclosed is a bipolar memory having redundancy, which can be produced with a small area. In this semiconductor memory having a body memory for storing data and a spare memory for relief of fault bit of the body memory, a row is selected by cutting fuses in a decoder. Fundamentally signal lines such as word lines are not provided with fuses. Other parts including a power source and a reference voltage source are provided with fuses without decreasing the operating speed accompanied by only a slight increase in the area.

Semiconductor memory having redundancy

A semiconductor circuit of a current mode type logic is provided having a reference voltage generating circuit which generates the reference voltage to be applied to the logic circuit in response to a clock signal to latch the state corresponding to an input signal at an instant of the clock signal input. The reference voltage has three levels in response to the voltage levels of the clock signal and the input signal: a middle voltage between the two high and low voltage levels of the input signal when the clock signal is at a first level voltage; a voltage higher than the high voltage level of the input signal when the clock signal is at a second level voltage and the output signal is at a high voltage; and a voltage lower than the low voltage level of the input signal when the clock signal is at a second level voltage and the output signal is at a second level voltage and the output signal is at a low voltage. This semiconductor circuit can relax restrictions on the signal amplitude due to the supply voltage and the saturation of the transistors, and, accordingly, allows processing signals having a much greater amplitude than was previously possible.

Semiconductor circuit having a current switch circuit which imparts a

Herein disclosed is a circuit for converting the logic amplitude of an ECL by logically amplifying a TTL or CMOS so that no substantial dc current flows in the steady state. The level converting circuit comprises: a level-shift circuit for generating a first output with a small level-shift and a second output with a larger level-shift than said first output; a CMOS circuit including a PMOS transistor having its gate fed with said first output, and an nMOS transistor having its gate fed with said second output; and a current switch for giving output levels to turn on said PMOS transistor and off said nMOS transistor at its high level and to turn on said PMOS transistor and off said nMOS transistor at its low level.

Level converter circuit

This invention is effective in the speeding up of a decoder circuit and maintenance of output amplitude. The invention is characterized in that, in a decoder circuit composed of a multi-emitter transistor or at least one diode group in which the anodes of a plurality of diodes are connected, and a charge circuit having an output emitter follower transistor, the multi-emitter transistor or the forward voltage of the diodes are larger than the voltage between the base and the emitter of the output emitter follower transistor.

Decoder circuit using transistors or diodes of different characteristics

Growing community of inventors

Kokubunji, Japan

Noriyuki Honma