Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Renesas Northern Japan Semiconductor, Inc.

Superh, Inc.

Other

Noriyoshi Watanabe

Masanao Yamaoka

Noriaki Maeda

Yoshihiro Shinozaki

Kazutomo Ogura

Kiyotada Funane

A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

Semiconductor memory device and semiconductor integrated circuit device

To a first signal line to which a signal with a comparable small amplitude against the power supply voltage is transmitted at a first timing, a second signal line to which a voltage maintained at a constant is transmitted at the first timing is laid out on the same wiring layer as that of the first signal line adjacently to each other. Thereby, the invention reduces the coupling noises without impairing a high density of the signal wirings, and provides a semiconductor integrated circuit device with a memory circuit that realizes a high integration, low power consumption, and high speed.

Semiconductor integrated circuit device with reduced coupling noise

A signal to be written is transmitted to said pairs of writing signal lines in parallel with address input operation for the selection of a word line, information stored in the memory cell selected in response to the selection operation of said word line is transmitted to said pair of reading signal lines via said second selecting switch circuit so that it is amplified by said sense amplifier, and the amplified output of said sense amplifier is compared with the signal to be written on said pair of writing signal lines so that the signal to be written is written into said selected memory cell by selectively turning on said first selecting switch circuit in response to a result of said comparison.

Semiconductor integrated circuit device including a cache having a comparator and a memory

Growing community of inventors

Chitose, Japan

Noriyoshi Watanabe