Adv Antest Corporation

Noriyoshi Kozuka

Hiroyuki Hama

Hiroyuki Nagai

Toshikazu Suzuki

Shigeru Matsumura

Koji Hara

Kohei Shibata

Hirokatsu Niijima

Takashi Sekizuka

Hiroyuki Shiotsuka

Yukio Ishigaki

Eiichi Sekine

Tetsuya Sakaniwa

There is provided a test apparatus for testing a device under test, including a plurality of operational units that operate in response to control data supplied thereto to test the device under test, a control section that generates packet data containing the control data and unit selection data indicating which one or more of the plurality of operational units are to be selected, and a plurality of data transfer units that are cascade-connected to each other so that the packet data is transferred from each of the plurality of data transfer units to a data transfer unit of a following stage, where each of the plurality of data transfer units corresponds to one or more of the plurality of operational units. Here, when each of the plurality of data transfer units receives the packet data whose unit selection data indicates that one or more of the operational units corresponding thereto are to be selected, the data transfer unit inputs the control data contained in the packet data into the selected operational units or reads data from the selected operational units.

Test apparatus and circuit apparatus

There is provided a test apparatus for testing a plurality of devices under test. The test apparatus includes a signal input section that applies a test signal to the devices under test so as to cause the devices under test to concurrently output response signals, a combining section that generates a single combination signal by using the response signals output from the devices under test, and a judging section that judges whether the devices under test operate normally with reference to the combination signal.

Test apparatus, test method and manufacturing method

A calibration method for calibrating a semiconductor testing apparatus before mounting semiconductor devices for performing a testing of electric characteristics thereof, the testing apparatus having a driver which generates and outputs a signal, and a socket with a plurality of terminals for receiving pins and transferring signals therethrough. The calibration method includes mounting a test board having a plurality of pins onto the socket and connecting each of the pins of the test board with a respective terminal of the socket, transferring the signal of the driver to the terminals of the test board, detecting the signal of the driver that has reached the test board, and setting an output timing of the signal of the driver based on the signal detected.

Semiconductor device testing apparatus and its calibration method

Growing community of inventors

Tokyo, Japan

Noriyoshi Kozuka